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MAX1072CTC(2004) 查看數據表(PDF) - Maxim Integrated

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MAX1072CTC Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ANALOG INPUTS (AIN+, AIN-)
Differential Input Voltage Range
Absolute Input Voltage Range
DC Leakage Current
Input Capacitance
Input Current (Average)
REFERENCE INPUT (REF)
AIN+ - AIN-, MAX1072
VIN
AIN+ - AIN-, MAX1075
0
-VREF / 2
VREF
V
+VREF / 2
0
VDD
V
±1
µA
Per input pin
20
pF
Time averaged at maximum throughput rate
75
µA
REF Input Voltage Range
VREF
1.0
VDD +
50mV
V
Input Capacitance
20
pF
DC Leakage Current
±1
µA
Input Current (Average)
Time averaged at maximum throughput rate
400
µA
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low
VIL
0.3 x VL V
Input Voltage High
VIH
0.7 x VL
V
Input Leakage Current
IIL
0.05 ±10
µA
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
COUT For stated timing performance
30
pF
Output Voltage Low
VOL
ISINK = 5mA, VL 1.8V
0.4
V
Output Voltage High
VOH
ISOURCE = 1mA, VL 1.8V
VL - 0.5V
V
Output Leakage Current
IOL
Output high impedance
±0.2 ±10
µA
POWER REQUIREMENTS
Analog Supply Voltage
VDD
4.75
5.25
V
Digital Supply Voltage
VL
1.8
VDD
V
Analog Supply Current,
Normal Mode
Static, fSCLK = 28.8MHz
IDD
Static, no SCLK
Operational, 1.8Msps
7
9
4
5
mA
9
11
Analog Supply Current,
Partial Power-Down Mode
IDD
fSCLK = 28.8MHz
No SCLK
1
mA
1
Analog Supply Current,
Full Power-Down Mode
Digital Supply Current (Note 7)
Positive-Supply Rejection
IDD
fSCLK = 28.8MHz
No SCLK
Operational, full-scale input at 1.8Msps
Static, fSCLK = 28.8MHz
Partial/full power-down mode,
fSCLK = 28.8MHz
Static, no SCLK (all modes)
PSR VDD = 5V ±5%, full-scale input
1
µA
1
1
2.5
0.4
1
mA
0.2
0.5
0.1
1
µA
±0.2 ±3.0
mV
_______________________________________________________________________________________ 3

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