MAX1072CTC(2004) 查看數據表（PDF） - Maxim Integrated

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MAX1072CTC
(Rev.:2004)

1.8Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs

Maxim Integrated 

1.8Msps, Single-Supply, Low-Power,

True-Differential, 10-Bit ADCs

TIMING CHARACTERISTICS

(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical

values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SCLK Pulse-Width High

SCLK Pulse-Width Low

SCLK Rise to DOUT Transition

DOUT Remains Valid After SCLK

CNVST Fall to SCLK Fall

CNVST Pulse Width

Power-Up Time; Full Power-Down

Restart Time; Partial Power-Down

tCH

tCL

tDOUT

tDHOLD

tSETUP

tCSW

TPWR-UP

tRCV

VL = 1.8V to VDD

VL = 1.8V to VDD

CL = 30pF, VL = 4.75V to VDD

CL = 30pF, VL = 2.7V to VDD

CL = 30pF, VL = 1.8V to VDD

VL = 1.8V to VDD

VL = 1.8V to VDD

VL = 1.8V to VDD

15.6

15.6

4

10

20

2

16

ns

ns

14

17

ns

24

ns

ns

ns

ms

Cycles

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset

error have been nulled.

Note 2: No missing codes over temperature.

Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.

Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.

Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-

ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.

Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.

Note 7: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.

CNVST

SCLK

tSETUP

DOUT

tCL tCH

tDHOLD

tDOUT

VL

tCSW

DOUT

6kΩ

DOUT

6kΩ

CL

GND

a) HIGH-Z TO VOH, VOL TO VOH,

AND VOH TO HIGH-Z

CL

GND

b) HIGH-Z TO VOL, VOH TO VOL,

AND VOL TO HIGH-Z

Figure 1. Detailed Serial-Interface Timing

Figure 2. Load Circuits for Enable/Disable Times

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