MAX1243 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8

Maxim Integrated 

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

TIMING CHARACTERISTICS

(VDD = +2.7V to +5.25V, circuit of Figure 9, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

Acquisition Time

SCLK Fall to Output Data Valid

CS Fall to Output Enable

CS Rise to Output Disable

SCLK Clock Frequency

SCLK Pulse Width High

SCLK Pulse Width Low

SCLK Low to CS Fall Setup Time

DOUT Rise to SCLK Rise (Note 6)

CS Pulse Width

SYMBOL

tACQ

tDO

tDV

tTR

fSCLK

tCH

tCL

tCS0

tSTR

tCS

CONDITIONS

CS = VDD (Note 8)

Figure 1,

CLOAD = 50pF

MAX124_ _C/E

Figure 1, CLOAD = 50pF

Figure 2, CLOAD = 50pF

MIN TYP MAX UNITS

1.5

µs

20

200

ns

240

ns

240

ns

0

2.1

MHz

200

ns

200

ns

50

ns

0

ns

240

ns

Note 1: Tested at VDD = +2.7V.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3: Offset nulled.

Note 4: Sample tested to 0.1% AQL.

Note 5: External load should not change during conversion for specified accuracy.

Note 6: Guaranteed by design. Not subject to production testing.

Note 7: Measured as [VFS (VDD(min)) - VFS (VDD(max))].

Note 8: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum

time needed for the signal to be acquired.

+2.7V

6kΩ

DOUT

6kΩ

DGND

a) High-Z to VOH and VOL to VOH

Figure 1. Load Circuits for DOUT Enable Time

CLOAD = 50pF

DOUT

CLOAD = 50pF

DGND

b) High-Z to VOL and VOH to VOL

+2.7V

6kΩ

DOUT

6kΩ

DGND

a) VOH to High-Z

Figure 2. Load Circuits for DOUT Disable Time

4

CLOAD = 50pF

DOUT

b) VOLto High-Z

CLOAD = 50pF

DGND

Maxim Integrated

Share Link: