MAX1215(2005) 查看數據表（PDF） - Maxim Integrated
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MAX1215 Datasheet PDF : 20 Pages
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1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω ±1%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low
VIL
Digital Input-Voltage High
VIH
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
tPDL
Figure 4
CLK-to-DCLK Propagation Delay
tCPDL Figure 4
DCLK-to-Data Propagation Delay tPDL - tCPDL Figure 4 (Note 3)
LVDS Output Rise Time
tRISE
20% to 80%, CL = 5pF
LVDS Output Fall Time
tFALL 20% to 80%, CL = 5pF
Output Data Pipeline Delay
tLATENCY Figure 4
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
(Note 3)
AVCC
OVCC
IAVCC
IOVCC
PDISS
PSRR
fIN = 100MHz
fIN = 100MHz
fIN = 100MHz
Offset
Gain
MIN TYP MAX UNITS
0.2 x AVCC V
0.8 x AVCC
V
1.75
ns
3.87
ns
1.66 2.12 2.48
ns
460
ps
460
ps
11
Clock
cycles
1.70 1.80 1.90
V
1.70 1.80 1.90
V
495
555
mA
64
75
mA
1006 1134 mW
1.8
mV/V
1.5
%FS/V
Note 1: ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are based on the end-point fit method. The full-scale range (FSR) is defined as 4095 x
slope of the line.
Note 3: Parameter guaranteed by design and characterization: TA = TMIN to TMAX.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
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