MAX17043 查看數據表（PDF） - Maxim Integrated
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MAX17043 Datasheet PDF : 14 Pages
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MAX17043/MAX17044
1-Cell/2-Cell Fuel Gauge with
ModelGauge and Low-Battery Alert
Electrical Characteristics: 2-Wire Interface
(2.5V ≤ VDD ≤ 4.5V, TA = -20°C to +70°C, unless otherwise noted.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA
and SCL Signals
Fall Time of Both SDA
and SCL Signals
Setup Time for STOP Condition
Spike Pulse Widths Suppressed
by Input Filter
Capacitive Load for Each
Bus Line
SCL, SDA Input Capacitance
SYMBOL
fSCL (Note 5)
tBUF
CONDITIONS
tHD:STA (Note 5)
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
(Notes 6, 7)
(Note 6)
tR
tF
tSU:STO
tSP
(Note 8)
CB
CBIN
(Note 9)
MIN TYP MAX UNITS
0
400
kHz
1.3
µs
0.6
1.3
0.6
0.6
0
100
20 +
0.1CB
20 +
0.1CB
0.6
0
µs
µs
µs
µs
0.9
µs
ns
300
ns
300
ns
µs
50
ns
400
pF
60
pF
Note 1: All voltages are referenced to GND.
Note 2: SDA, SCL = GND; QSTRT, ALRT idle.
Note 3: The MAX17043/MAX17044 enter Sleep mode 1.75s to 2.5s after (SCL < VIL) AND (SDA < VIL).
Note 4: Time to enter sleep after Sleep command is sent. Time to exit sleep on rising edge of SCL or SDA.
Note 5: fSCL must meet the minimum clock low time plus the rise/fall times.
Note 6: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 9: CB—total capacitance of one bus line in pF.
Note 10: Applies to 8-pin TDFN-EP package type only.
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