MAX17435 查看數據表（PDF） - Maxim Integrated

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MAX17435

High-Frequency, Low-Cost SMBus Chargers

Maxim Integrated 

High-Frequency,

Low-Cost SMBus Chargers

Ideally, surface-mount power components are flush

against one another with their ground terminals

almost touching. These high-current grounds are then

connected to each other with a wide, filled zone of

top-layer copper, so they do not go through vias. The

resulting top-layer subground plane is connected to

the normal inner-layer ground plane at the paddle.

Other high-current paths should also be minimized,

but focusing primarily on short ground and current-

sense connections eliminates about 90% of all PCB

layout problems.

2) Place the IC and signal components. Keep the

main switching node (LX node) away from sensitive

analog components (current-sense traces and VAA

capacitor). Important: The IC must be no further

than 10mm from the current-sense resistors. Quiet

connections to VAA, CC, ACIN, and DCIN should

be returned to a separate ground (GND) island. The

appropriate traces are marked on the schematic with

the () ground symbol. There is very little current flowing

in these traces, so the ground island need not be

very large. When placed on an inner layer, a sizable

ground island can help simplify the layout because

the low current connections can be made through

vias. The ground pad on the backside of the package

should also be connected to this quiet ground island.

3) Keep the gate drive traces (DHI and DLO) as short

as possible (L < 20mm), and route them away from

the current-sense lines and REF. These traces should

also be relatively wide (W > 1.25mm).

4) Place ceramic bypass capacitors close to the IC. The

bulk capacitors can be placed further away. Place the

current-sense input filter capacitors under the part,

connected directly to the GND pin.

5) Use a single-point star ground placed directly below

the part at the PGND pin. Connect the power ground

(ground plane) and the quiet ground island at this

location.

Refer to the MAX17435 and MAX17535 Evaluation Kit

layouts for a layout example.

PROCESS: BiCMOS

Chip Information

Package Information

For the latest package outline information and land patterns,

go to www.maxim-ic.com/packages. Note that a “+”, “#”, or

“-” in the package code indicates RoHS status only. Package

drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

PACKAGE

TYPE

24 TQFN-EP

PACKAGE

CODE

T2444+3

OUTLINE

No.

21-0139

LAND

PATTERN No.

90-0021

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