MAX19707ETM 查看數據表（PDF） - Maxim Integrated
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MAX19707ETM Datasheet PDF : 37 Pages
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10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS
CONDITIONS
MIN TYP MAX UNITS
Receive Transmit Isolation
AUXILIARY ADC (ADC1, ADC2)
Resolution
Full-Scale Reference
N
VREF
Analog Input Range
Analog Input Impedance
Input-Leakage Current
Gain Error
GE
Zero-Code Error
ZE
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Supply Current
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution
N
Integral Nonlinearity
INL
ADC fINI = fINQ = 5.5MHz, DAC fOUTI =
fOUTQ = 2.2MHz, fCLK = 45MHz
AD1 = 0 (default)
AD1 = 1
At DC
Measured at unselected input from 0 to
VREF
Includes reference error
(Note 6)
85
dB
10
2.048
VDD
0 to
VREF
500
±0.1
-5
+5
2
±0.53
±0.45
210
12
±1.25
Bits
V
V
kΩ
µA
%FS
mV
LSB
LSB
µA
Bits
LSB
Differential Nonlinearity
DNL
Guaranteed monotonic over codes 100 to
4000 (Note 6)
-1.0 ±0.65 +1.1
LSB
Gain Error
GE
Zero-Code Error
ZE
Output-Voltage Low
VOL
Output-Voltage High
VOH
DC Output Impedance
Settling Time
Glitch Impulse
Rx ADC–Tx DAC TIMING CHARACTERISTICS
CLK Rise to Channel-I Output Data
Valid
tDOI
RL > 200kΩ
RL > 200kΩ
RL > 200kΩ
DC output at midscale
From 1/4 FS to 3/4 FS, within ±10 LSB
From 0 to FS transition
Figure 3 (Note 6)
±0.7
%FS
±0.6
%FS
0.1
V
2.56
V
4
Ω
1
µs
24
nV•s
5.4
6.5
8.1
ns
CLK Fall to Channel-Q Output
Data Valid
tDOQ Figure 3 (Note 6)
7.3
8.8 11.1
ns
I-DAC DATA to CLK Fall Setup
Time
tDSI
Figure 5 (Note 6)
9
ns
6 _______________________________________________________________________________________
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