MAX19707ETM 查看數據表（PDF） - Maxim Integrated

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MAX19707ETM

10-Bit, 45Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

10-Bit, 45Msps, Ultra-Low-Power

Analog Front-End

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =

CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN)

MIN TYP MAX UNITS

Input High Threshold

Input Low Threshold

VINH

VINL

0.7 x OVDD

V

0.3 x OVDD V

Input Leakage

DIIN

D0–D9, CLK, SCLK, DIN, CS, T/R,

SHDN = OGND or OVDD

-1

+1

µA

Input Capacitance

DCIN

DIGITAL OUTPUTS (D0–D9, DOUT)

5

pF

Output-Voltage Low

Output-Voltage High

VOL

VOH

ISINK = 200µA

ISOURCE = 200µA

0.2 x OVDD V

0.8 x OVDD

V

Tri-State Leakage Current

Tri-State Output Capacitance

ILEAK

COUT

-1

+1

µA

5

pF

Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are

guaranteed by design and characterization.

Note 2: The minimum clock frequency (fCLK) for the MAX19707 is 7.5MHz (typical). The minimum aux-ADC sample rate clock fre-

quency (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK >

7.5MHz / 128 = 58.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI™.

The maximum conversion time (for no averaging, NAVG = 1) will be, tCONV (max) = (12 x 1 x 128) / 7.5MHz = 205µs.

Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude

of the digital outputs. SINAD and THD are calculated using HD2 through HD6.

Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second

channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel

FFT test tone.

Note 5: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output

signals using a sine-wave fit.

Note 6: Guaranteed by design and characterization.

SPI is a trademark of Motorola, Inc.

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