MAX3681EAG(1996) 查看數據表（PDF） - Maxim Integrated
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MAX3681EAG Datasheet PDF : 8 Pages
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+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1, 2, 5, 8, 12
3
VCC
SD+
+3.3V Supply Voltage
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
SCLK+
Noninverting PECL Serial Clock Input
7
SCLK-
Inverting PECL Serial Clock Input
9, 15, 22
GND
Ground
10
SYNC+
Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
11
SYNC-
Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
13
PCLK-
Inverting LVDS Parallel Clock Output
14
PCLK+
Noninverting LVDS Parallel Clock Output
16, 18, 20, 23
PD0- to PD3-
Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
17, 19, 21, 24
PD0+ to PD3+
Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
_______________Detailed Description
The MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
SD+
PECL
SD-
SCLK+
SCLK- PECL
SYNC+
SYNC-
100Ω LVDS
4-BIT
SHIFT
REGISTER
4-BIT
PARALLEL
OUTPUT
REGISTER
MAX3681
2-BIT
COUNTER
LVDS
LVDS
LVDS
LVDS
LVDS
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
Figure 1. Functional Diagram
4 _______________________________________________________________________________________
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