+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
VCC
PECL
LEVELS
RT*
RT*
0.1µF 25Ω
SDI+
50Ω 50Ω
0.1µF
100Ω
25Ω
SDI-
MAX3831
MAX3832
*SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL
IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
Figure 8. PECL-to-CML Interface
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3831/MAX3832 high-speed inputs
and outputs.
Place power-supply decoupling as close to VCC as
possible. To reduce feedthrough, take care to isolate
the input signals from the output signals.
VCC = 3.3V
VCC = 3.3V
PECL
OUTPUT
82Ω
SDI+
82Ω
82Ω
SDI-
82Ω
50Ω 50Ω
MAX3831
MAX3832
Figure 9. Direct Coupling of a PECL Output into the MAX3831/
MAX3832
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