MAX3831 查看數據表（PDF） - Maxim Integrated

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MAX3831

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator

Maxim Integrated 

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to

+85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

TTL INPUTS AND OUTPUTS

Input Voltage High

VIH

Input Voltage Low

VIL

Input Current High

IIH

VIH = 2.0V

Input Current Low

IIL

VIL = 0

Output Voltage High

VOH IOH = 20µA

Output Voltage Low

VOL IOL = 2mA

Output Impedance

TRIEN = GND

Note 2: When TEST = GND, the pattern generator will consume an additional 30mA.

Note 3: Guaranteed by design and characterization.

2.0

V

0.8

V

-250

-50

µA

-550

-100

µA

2.4

V

0.4

V

6

kΩ

AC ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to

+85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) (Note 4)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

4:1 MULTIPLEXER WITH CLOCK GENERATOR

Parallel Input Data Rate

622.08

Mbps

Maximum Parallel Input Skew

Serial-Data Output Rate

tes

(Note 5)

±7.5

2.48832

ns

Gbps

Serial-Data Output Rise/Fall Time

Serial-Data Output Random Jitter

tr, tf 20% to 80%

SRJ (Note 6)

120

ps

3.5 psRMS

40

psp-p

Serial-Data Output Deterministic

Jitter

SDJ (Note 7)

8

18

psp-p

1:4 DEMULTIPLEXER

Serial-Data Input Rate

Serial-Data Setup Time

Serial-Data Hold Time

Parallel-Data Output Rate

Parallel-Clock Output Frequency

PCLKO to PDO_ Delay

LVDS Output Rise/Fall Time

LVDS Differential Skew

LVDS Channel-to-Channel Skew

LVDS Three-State Enable Time

tSU

tH

PDO±

PCLKO±

tCLK-Q

tSKEW1

tSKEW2

Figure 3

Figure 3

MAX3831

MAX3832

MAX3831, Figure 3

20% to 80%

Any differential pair

PDO1± to PDO4±

2.48832

100

100

622.08

622.08

155.52

-100

90

300

350

65

<100

30

Gbps

ps

ps

Mbps

MHz

ps

ps

ps

ps

ns

Note 4: AC characteristics are guaranteed by design and characterization.

Note 5: Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset.

Note 6: Measured with a reference clock jitter of <1psRMS.

Note 7: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.

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