+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
PDO+
D
PDO-
VPDO-
SINGLE-ENDED OUTPUT
VPDO+
DIFFERENTIAL OUTPUT
0V (DIFF)
RL = 100Ω
|VOD|
Figure 1. Definition of the LVDS Output
SDI+
SDI-
(SDI+) - (SDI-)
V VOD
VOH
VOS
VOL
+VOD
0V
-VOD
VODp-p = VPDO+ - VPDO-
200mV MIN
600mV MAX
VID
400mVp-p MIN
1200mVp-p MAX
Figure 2. Definition of the CML Input
SCLKI
SDI
tSCLK = 1 / fSCLK
tSU
tH
PCLKO
PDO1–PDO4
tCLK-Q
NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).
Figure 3. Timing Parameters
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