MAX3880(1999) 查看數據表（PDF） - Maxim Integrated

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MAX3880
(Rev.:1999)

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

Pin Description

PIN

1, 17, 25, 33,

41, 49, 56,

62, 64

2

3

4, 7, 10, 13,

24, 32, 40,

48, 57

5

NAME

GND

FIL+

FIL-

VCC

PHADJ+

6

PHADJ-

8

SDI+

9

SDI-

11

SLBI+

12

SLBI-

14

SIS

15

SYNC-

16

18

19

20, 22, 26,

28, 30, 34,

36, 38, 42,

44, 46, 50,

52, 54, 58, 60

21, 23, 27,

29, 31, 35,

37, 39, 43,

45, 47, 51,

53, 55, 59, 61

63

SYNC+

PCLK-

PCLK+

PD0- to

PD15-

PD0+ to

PD15+

LOL

EP

Exposed Pad

FUNCTION

Ground

Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

+3.3V Supply Voltage

Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not

used.

Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not

used.

Positive Serial Data Input. 2.488Gbps data stream.

Negative Serial Data Input. 2.488Gbps data stream.

Positive System Loopback Input. 2.488Gbps data stream.

Negative System Loopback Input. 2.488Gbps data stream.

Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input

(SLBI).

Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data

bit periods (1.6ns) to shift the data alignment by dropping 1 bit.

Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data

bit periods (1.6ns) to shift the data alignment by dropping 1 bit.

Negative Parallel Clock LVDS Output

Positive Parallel Clock LVDS Output

Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK

signal (Figure 5).

Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK

signal (Figure 5).

Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pull-up resistor). The

LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.

Ground. This must be soldered to a circuit board for proper thermal performance (see Package

Information).

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