MAX3880 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

MAX3880

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

PCLK

PD0–PD15

tCLK-Q

MAX3880

3.3V

PHADJ+ (PIN 5)

NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-).

Figure 5. Timing Parameters

PHADJ- (PIN 6)

Low-Voltage Differential-Signal (LVDS)

Inputs and Outputs

The MAX3880 features LVDS inputs and outputs for

interfacing with high-speed digital circuitry. The LVDS

standard is based on the IEEE 1596.3 LVDS specifica-

tion. This technology uses 500mVp-p to 800mVp-p dif-

ferential low-voltage swings to achieve fast transition

times, minimize power dissipation, and improve noise

immunity. For proper operation, the parallel clock and

data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-)

require 100Ω differential DC termination between the

positive and negative outputs. Do not terminate these

outputs to ground. The synchronization LVDS inputs

(SYNC+, SYNC-) are internally terminated with 100Ω

differential input resistance and therefore do not require

external termination.

Design Procedure

Jitter Tolerance and Input

Sensitivity Trade-Offs

When the received data amplitude is higher than

50mVp-p, the MAX3880 provides a typical jitter toler-

ance of 0.46 UI at jitter frequencies greater than

10MHz. The SDH/SONET jitter tolerance specification is

0.15UI, leaving a jitter allowance of 0.31UI for receiver

preamplifier and postamplifier design.

The BER is better than 1 x 10-10 for input signals

greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will

be degraded, but will still be above the SDH/SONET

requirement. Trade-offs can be made between jitter tol-

erance and input sensitivity according to the specific

application. See the Typical Operating Characteristics

for Jitter Tolerance and BER vs. Input Voltage graphs.

Figure 6. Phase-Adjust Resistor-Divider

Applications Information

Consecutive Identical Digits (CIDs)

The MAX3880 has a low phase and frequency drift in

the absence of data transitions. As a result, long runs of

consecutive zeros and ones can be tolerated while

maintaining a BER of 1 x 10-10. The CID tolerance is

tested using a 213 - 1 pseudorandom bit stream

(PRBS), substituting a long run of zeros to simulate the

worst case. A CID tolerance of greater than 2,000 bits

is typical.

Phase Adjust

The internal clock is aligned to the center of the data

eye. For specific applications, this sampling position

can be shifted using the PHADJ inputs to optimize BER

performance. The PHADJ inputs operate with differen-

tial input voltages up to ±1.5V. A simple resistor-divider

with a bypass capacitor is sufficient to set these levels

(Figure 6). When the PHADJ inputs are not used, they

should be tied directly to VCC.

System Loopback

The MAX3880 is designed to allow system loopback

testing. The user can connect a serializer output

(MAX3890) in a transceiver directly to the SLBI+ and

SLBI- inputs of the MAX3880 for system diagnostics. To

select the SLBI± inputs, apply a TTL logic high to the

SIS pin.

8 _______________________________________________________________________________________

Share Link: