MAX3885 查看數據表（PDF） - Maxim Integrated
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MAX3885 Datasheet PDF : 8 Pages
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+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Pin Description
PIN
1, 2, 8, 16, 17,
24, 32, 33, 41,
48, 49, 57, 64
3, 5, 7, 9, 11,
13, 25, 34, 42,
47, 56
4
6
10
12
14
15
18
19
20, 22, 26, 28,
30, 35, 37, 39,
43, 45, 50, 52,
54, 58, 60, 62
21, 23, 27, 29,
31, 36, 38, 40,
44, 46, 51, 53,
55, 59, 61, 63
NAME
GND
VCC
SD+
SD-
SCLK+
SCLK-
SYNC-
SYNC+
PCLK-
PCLK+
PD0- to PD15-
PD0+ to PD15+
Ground
FUNCTION
+3.3V Supply Voltage
Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transi-
tion.
Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.
Serial Clock Noninverting PECL Input
Serial Clock Inverting PECL Input
Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK
periods to shift the data alignment by dropping one bit.
Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four
SCLK periods to shift the data alignment by dropping one bit.
Parallel Clock Inverting LVDS Output
Parallel Clock Noninverting LVDS Output
Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK
signal.
Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the
PCLK signal.
PD+
D
PD-
VPD-
SINGLE-ENDED OUTPUT
VPD+
VPD+ - VPD-
DIFFERENTIAL OUTPUT
0V (DIFF.)
RL = 100Ω
|VOD|
V VOD
VOH
VOS
VOL
+VOD
0V
-VOD
VOD, P - P = VPD+ - VPD-
Figure 1. Driver Output Levels
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