MAX3885 查看數據表（PDF） - Maxim Integrated

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MAX3885

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with LVDS Outputs

SCLK

SD

tSCLK = 1 / fSCLK

tSU

tH

PCLK

PD0–PD15

tCLK-Q

NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).

Figure 4. Timing Parameters

DC termination between the inverting and noninverting

outputs for proper operation. Do not terminate these

outputs to ground. The synchronization LVDS inputs

(SYNC+, SYNC-) are internally terminated with 100Ω

differential input resistance and, therefore, do not

require external termination.

PECL Inputs

Because of the self-biasing resistor networks, the serial

data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-)

require 53Ω termination to VCC - 2V when interfacing

with a PECL source (see Alternative PECL Input

Termination). This results in an equivalent input resis-

tance of 50Ω.

Applications Information

Alternative PECL Input Termination

Figure 5 shows alternative PECL input-termination

methods. Use Thevenin-equivalent termination when a

VCC - 2V termination voltage is not available. When

interfacing with an ECL-output device, the MAX3885’s

internal self-biasing allows easy ECL AC-coupling ter-

mination.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies and keep ground

connections short. Use multiple vias where possible.

Also, use controlled impedance transmission lines to

interface with the MAX3885 high-speed inputs and out-

puts.

THEVENIN-EQUIVALENT TERMINATION

+3.3V

133Ω

ZO = 50Ω

133Ω

MAX3885

ZO = 50Ω

PECL

INPUTS

86.6Ω

86.6Ω

ECL AC-COUPLING TERMINATION

ZO = 50Ω

MAX3885

ZO = 50Ω

53Ω

-2V

PECL

INPUTS

53Ω

-2V

Figure 5. Alternative PECL Input Termination

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