MAX4003ETA-T 查看數據表（PDF） - Maxim Integrated

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MAX4003ETA-T

100MHz to 2500MHz, 45dB RF Detector in a UCSP

Maxim Integrated 

100MHz to 2500MHz, 45dB RF Detector

in a UCSP

PIN

µMAX/

UCSP

Thin QFN

1

A1

2

A2

3, 5

A3, C3

4

B3

6

—

7

C2

8

B1, C1

Pin Description

NAME

DESCRIPTION

RFIN

SHDN

GND

CLPF

N.C.

OUT

VCC

RF Input. Requires off-chip 50Ω impedance match.

Shutdown Input. A logic LOW on SHDN shuts down the entire IC.

Ground. Connect to PC board ground plane.

Lowpass Filter Connection. Connect external capacitor between CLPF and GND to set the

control-loop bandwidth.

No Connection. Leave this pin unconnected or connect to GND.

Detector Output. Connect this buffer output to baseband ADC.

Supply Voltage. Bypass with capacitor as close to the pin as possible. The bypass capacitor

must not share its ground vias with any other branches.

Detailed Description

The MAX4003 logarithmic amplifier comprises four

main amplifier/limiter stages, each with a small-signal

gain of 10dB. The output stage of each amplifier/limiter

stage is applied to a full-wave rectifier (detector). A

detector stage also precedes the first stage. In total,

five detectors, each separated by 10dB, comprise the

logarithmic amplifier strip (see Functional Diagram).

A portion of the PA output power is coupled into RFIN

of the logarithmic amplifier detector through a direction-

al coupler, and is applied to the logarithmic amplifier

strip. Each detector stage generates a rectified current,

and these currents are summed to form a logarithmic

function. The detected output is applied to a high-gain

transconductance (gm) stage, which is buffered and

then applied to OUT. OUT is applied to an ADC typical-

ly found in the baseband IC which, in turn, controls the

XX

50Ω

50Ω

PA

TRANSMITTER

MAX4003

RFIN

VCC

SHDN

OUT

GND

N.C.

DAC

VCC

0.01µF

BASEBAND

IC

ADC

CLPF

GND

CCLPF

Figure 1. MAX4003 Typical Application Circuit

PA biasing with its DAC output (Figure 1).

In a control loop, the detector output voltage range is

approximately 0.36V for the minimum input signal,

-45dBm, to 1.45V at the maximum input range, 0dBm.

The logarithmic intercept of the detector output with

respect to the RF input can be obtained by drawing a

best fit line of the Output Voltage vs. RF Input Power

graph. The logarithmic slope is defined as the change

in the detector output vs. the change in RF input. The

MAX4003 slope at low frequencies is approximately

25.5mV/dB. Variation in temperature and supply volt-

age does not alter the slope significantly, as shown in

the Typical Operating Characteristics.

Applications Information

Filter Capacitor and Transient Response

In general, the choice of filter only partially determines

the time-domain response of a PA detector loop.

However, some simple conventions may be applied to

discuss transient response. A large filter capacitor,

CCLPF, dominates time-domain response, but the loop

bandwidth remains a factor of the PA gain-control range

(see Typical Operating Characteristics). The bandwidth

is maximized at power outputs near the center of the

PA’s range and minimized at the low and high power lev-

els, when the slope of the gain control curve is lowest.

A smaller valued CCLPF results in an increased-loop

bandwidth inversely proportional to the capacitor value.

Inherent phase lag in the PA’s control path, usually

caused by parasitics at the OUT pin, ultimately results

in the addition of complex poles in the AC loop equa-

tion. To avoid this secondary effect, experimentally

determine the lowest usable CCLPF for the power ampli-

8 _______________________________________________________________________________________

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