MAX4675 查看數據表（PDF） - Maxim Integrated
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MAX4675 Datasheet PDF : 8 Pages
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3Ω Single SPST Analog Switches
Applications Information
Overvoltage Protection
Proper power-supply sequencing is recommended for all
CMOS devices. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can
cause permanent damage to the devices. Always
sequence V+ on first, then V-, followed by the logic
inputs, NO, NC, or COM. If proper power-supply
sequencing is not possible, add two small-signal diodes
(D1, D2) in series with the supply pins (Figure 1). Adding
diodes reduces the analog signal range to one diode
drop below V+ and one diode drop above V- but does
not affect the devices’ low switch resistance and low
leakage characteristics. Device operation is unchanged,
and the difference between V+ and V- should not
exceed 12V.
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1µF capacitor connect-
ed from V+ to GND is adequate for most applications.
V+
Vg
V-
Figure 1. Overvoltage Protection Using External Blocking
Diodes
Timing Diagrams/Test Circuits
MAX4675
MAX4676
SWITCH
INPUT
NO
OR NC
IN
LOGIC
GND
INPUT
V+
V+
COM
V-
V-
SWITCH
OUTPUT
VOUT
RL
300Ω
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VCOM
RL
RL + RON
Figure 2. Switching Time
MAX4675
MAX4676
VGEN
RGEN NC
OR NO
GND
V+
V+
COM
IN V-
VOUT
CL
V-
VIN = 3.0V
Figure 3. Charge Injection
+3V
LOGIC
INPUT 0
tr < 20ns
tf < 20ns
50%
50%
SWITCH 0
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
_______________________________________________________________________________________ 7
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