MAX4929E 查看數據表（PDF） - Maxim Integrated
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MAX4929E Datasheet PDF : 13 Pages
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HDMI 2:1 Low-Frequency Translating Switch
PIN
QSOP
TQFN
1
19
2
20
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
11
14
12
15
13
16
14
17
15
18
16
19
17
20
18
—
EP
Pin Description
NAME
FUNCTION
HPDO2
HPIR2
SDA2
SCL2
HPDO1
HPIR1
SDA1
SCL1
V+
CLP
VL
SEL
SCLO
SDAO
HPIRO
HPD
HIZ2
HIZ1
GND
EXESD
EP
Hot-Plug Detect Output 2. Translate logic level of HPD to V+ compatible (see Table 2).
Hot-Plug Interrupt Request 2
Serial Data Input. SDA Mux Input 2.
Serial Clock Input. SCL Mux Input 2.
Hot-Plug Detect Output 1. Translate logic level of HPD to V+ compatible (see Table 2).
Hot-Plug Interrupt Request 1
Serial Data Input. SDA Mux Input 1.
Serial Clock Input. SCL Mux Input 1.
Positive Supply Voltage. Bypass V+ to GND with a 0.1µF or greater ceramic capacitor.
Clamp-Voltage Reference. Clamp the maximum voltage of SCLO and SDAO. Bypass
CLP to GND with a 0.1µF or greater ceramic capacitor (see Figure 6 and the Typical
Operating Circuit).
Logic Supply for HIZ_, SEL, HPD, HPIRO. Bypass VL to GND with a 0.1µF or greater
ceramic capacitor. VL should have the same voltage level as any MCU interface.
Select Input. Logic input for Mux connection (see Table 1).
SCL Mux Output. Connect SCLO to EDID EPROM.
SDA Mux Output. Connect SDAO to EDID EPROM.
Hot-Plug Interrupt Request Output. Translate logic level of HPIR_ to VL compatible
(see Table 3).
Hot-Plug Detect Input. Logic level on HPD is compatible with MCU.
Enable Input 2 (see Table 4).
Enable Input 1 (see Table 4).
Ground
External ESD Discharge. Connect 0.1µF capacitor from EXESD to GND.
Exposed Paddle. Connect EP to GND or leave EP unconnected.
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