MAX500 查看數據表（PDF） - Maxim Integrated
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MAX500 Datasheet PDF : 12 Pages
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CMOS, Quad, Serial-Interface
8-Bit DAC
Using an AC Reference
In applications where VREF has AC signal components,
the MAX500 has multiplying capability within the limits
of the VREF input range specifications. Figure 11 shows
a technique for applying a sine-wave signal to the refer-
ence input, where the AC signal is biased up before
being applied to VREF. Output distortion is typically less
than 0.1% with input frequencies up to 50kHz, and the
typical -3dB frequency is 700kHz. Note that VREF must
never be more negative than AGND.
Generating VSS
The performance of the MAX500 is specified for both
dual and single-supply (VSS = 0V) operation. When the
improved performance of dual-supply operation is
desired, but only a single supply is available, a -5V VSS
supply can be generated using an ICL7660 in one of
the circuits of Figure 12.
Digital Interface Applications
Figures 13 through 16 show examples of interfacing the
MAX500 to most popular microprocessors.
+15V
15k
AC
REFERENCE
INPUT
+4V
10k
-4V
4
VREFA/B
DAC B
VSS
3
-5V (OR GND)
AGND
5
DIGITAL INPUTS NOT SHOWN
Figure 11. AC Reference Input Circuit
14
VDD
VOUTB 1 VOUTB
MAX500
DGND
6
12V to 15V
10k
2N2222
6V
ZENER
10k 10µF
10µF
2
4
CAP+
CAP-
8
V+
3
ICL7660
GND
VOUT
5
+5V
LOGIC
SUPPLY
-5V
VSS OUT
10µF
10µF
2
4
CAP+
CAP-
8
V+
3
ICL7660
GND
VOUT
5
-5V
VSS OUT
10µF
Figure 12. Generating -5V for VSS
80C51
P1.0
P1.1
P1.2
P1.3 . . . . . . .
MAX500
SCL
SRO
SDA
LDAC
LOAD*
VOUTA
VOUTB
VOUTC
VOUTD
VREFA/B
VREFC
VREFD
A15
A0
Z80
I/O REQ
WR
INT
D7
D0
ADDRESS BUS
EN
ADDRESS
CODE
A1 A0 B/A Z8420
C/D B0
SCL MAX500
CE B1
SDA
RD
B2
LDAC
INT
D7 B3 . . LOAD*
D0
DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 13. 80C51 Interface
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 14. Z-80 with Z8420 PIO Interface
______________________________________________________________________________________ 11
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