MAX5054 查看數據表（PDF） - Maxim Integrated

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MAX5054

4A, 20ns, Dual MOSFET Drivers

Maxim Integrated 

4A, 20ns, Dual MOSFET Drivers

IN_+

VIH

VIL

90%

OUT_

tD-OFF1

10%

tD-ON1

tF

tR

IN_- VIH

tD-OFF2

VIL

tD-ON2

RISING MISMATCH = tD-ON2 - tD-ON1

FALLING MISMATCH = tD-OFF2 - tD-OFF1

Figure 1. Timing Diagram

MAX5054

IN_-

IN_+

BREAK-

BEFORE-

MAKE

CONTROL

VDD

P

OUT_

N

GND

MAX5055

MAX5056

MAX5057

IN_+

BREAK-

BEFORE-

MAKE

CONTROL

NONINVERTING INPUT DRIVER

MAX5055

MAX5056

MAX5057

IN_-

BREAK-

BEFORE-

MAKE

CONTROL

INVERTING INPUT DRIVER

VDD

P

OUT_

N

GND

VDD

P

OUT_

N

GND

Figure 2. MAX5054 Block Diagram (1 Driver)

Detailed Description

VDD Undervoltage Lockout (UVLO)

The MAX5054–MAX5057 have internal undervoltage

lockout for VDD. When VDD is below the UVLO thresh-

old, OUT_ is low, independent of the state of the inputs.

The undervoltage lockout is typically 3.5V with 200mV

typical hysteresis to avoid chattering. When VDD rises

above the UVLO threshold, the outputs go high or low

depending upon the logic-input levels. Bypass VDD

using low-ESR ceramic capacitors for proper operation

(see the Applications Information section).

Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams

(1 Driver)

Logic Inputs

The MAX5054B–MAX5057 have TTL-compatible logic

inputs, while the MAX5054A is a CMOS logic-input dri-

ver. The logic-input signals can be independent of the

VDD voltage. For example, the device can be powered

by a 5V supply while the logic inputs are provided from

CMOS logic. Also, the logic inputs are protected against

the voltage spikes up to 18V, regardless of the VDD volt-

age. The TTL and CMOS logic inputs have 300mV and

0.1 x VDD hysteresis, respectively, to avoid possible dou-

ble pulsing during transition. The low 2.5pF input capaci-

tance reduces loading and increases switching speed.

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