MAX5072ETJ 查看數據表（PDF） - Maxim Integrated

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MAX5072ETJ

2.2MHz, Dual-Output Buck or Boost Converter with POR and Power-Fail Output

Maxim Integrated 

2.2MHz, Dual-Output Buck or Boost

Converter with POR and Power-Fail Output

ABSOLUTE MAXIMUM RATINGS

V+ to PGND............................................................-0.3V to +25V

SGND to PGND .....................................................-0.3V to +0.3V

SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms

VL, BYPASS to SGND Short Circuit............................Continuous

VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V)

BST1/VDD1, BST2/VDD2, DRAIN_, PFO, RST, PGOOD1 to

SGND .................................................................-0.3V to +30V

BST1/VDD1 to SOURCE1,

Continuous Power Dissipation (TA = +70°C)

32-Pin Thin QFN (derate 21.3mW/°C above +70°C).....2758mW*

Package Junction-to-Case Thermal Resistance (θJC).......2°C/W

Operating Temperature Ranges:

BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V

SOURCE_ to SGND................................................-0.6V to +25V

EN_ to SGND ................................................-0.3V to (VL + 0.3V)

MAX5072ETJ (TMIN to TMAX)...........................-40°C to +85°C

MAX5072ATJ (TMIN to TMAX).........................-40°C to +125°C

Junction Temperature ......................................................+150°C

CLKOUT, BYPASS, OSC, FSEL1, COMP1,

COMP2, PFI, MR, SYNC, FB_ to SGND....-0.3V to (VL + 0.3V)

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms

*As per JEDEC51 standard.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),

ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SYSTEM SPECIFICATIONS

Input Voltage Range

(Note 2)

V+

VL = V+

5.5

23

V

4.5

5.5

Operating Supply Current

V+ Standby Supply Current

Efficiency

STARTUP/VL REGULATOR

VL Undervoltage Lockout Trip

Level

IQ

ISTBY

η

VL unloaded, no switching,

VFB_ = 1V, V+ = 12V, ROSC = 60kΩ

EN_ = 0, MR, PFO, and PGOOD_ floating,

V+ = 12V, ROSC = 60kΩ (MAX5072ETJ)

EN_ = 0, MR, PFO, and PGOOD_ floating,

V+ = 12V, ROSC = 60kΩ (MAX5072ATJ)

VOUT1 = 3.3V at 1.5A,

VOUT2 = 2.5V at 0.75A

(fSW = 1.25MHz)

V+ = VL = 5V

V+ = 12V

V+ = 16V

2.2

1.2

mA

0.6

1.4

mA

0.6

1.4

82

80

%

78

UVLO VL falling

3.95

4.1

4.25

V

VL Undervoltage Lockout

Hysteresis

VL Output Voltage

BYPASS OUTPUT

BYPASS Voltage

BYPASS Load Regulation

SOFT-START

VL

V+ = 5.5V to 23V, ISOURCE = 0 to 40mA

175

mV

4.9

5.2

5.5

V

VBYPASS

IBYPASS = 0, ROSC = 60kΩ (MAX5072ETJ)

IBYPASS = 0, ROSC = 60kΩ (MAX5072ATJ)

1.98

1.975

2.00

2.00

2.02

2.025

V

∆VBYPASS 0 ≤ IBYPASS ≤ 50µA, ROSC = 60kΩ

0

2

10

mV

Digital Ramp Period

Internal 6-bit DAC

2048

fOSC

clock

cycles

Soft-Start Steps

64

steps

2 _______________________________________________________________________________________

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