ML6516244CR 查看數據表（PDF） - Micro Linear Corporation
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ML6516244CR Datasheet PDF : 12 Pages
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ARCHITECTURAL DESCRIPTION
The ML6516244 is a 16-bit buffer/line driver with 3-state
outputs designed for 3.0V to 3.6V and 4.5V to 5.5V VCC
operation. This device is designed for Quad-Nibble,
Dual-Byte or single 16-bit word memory interleaving
operations. Each bank has an independently controlled 3-
state output enable pin with output enable/disable access
times of less than 7.0ns. Each bank is configured to have
four independent buffer/line drivers.
Until now, these buffer/line drivers were typically
implemented in CMOS logic and made to be TTL
compatible by sizing the input devices appropriately. In
order to buffer large capacitances with CMOS logic, it is
necessary to cascade an even number of inverters, each
successive inverter larger than the preceding, eventually
leading to an inverter that will drive the required load
capacitance at the required frequency. Each inverter stage
represents an additional delay in the gating process
because in order for a single gate to switch, the input must
slew more than half of the supply voltage. The best of
these 16-bit CMOS buffers has managed to drive 50pF
load capacitance with a delay of 3.6ns.
Micro Linear has produced a 16-bit buffer/line driver with
a delay less than 2.5ns by using a unique circuit
architecture that does not require cascade logic gates.
The basic architecture of the ML6516244 is shown in
Figure 11. In this circuit, there are two paths to the output.
ML6516244
One path sources current to the load capacitance where
the signal is asserted, and the other path sinks current from
the output when the signal is negated.
The assertion path is the Darlington pair consisting of
transistors Q1 and Q2. The effect of transistor Q1 is to
increase the current gain through the stage from input to
output, to increase the input resistance and to reduce
input capacitance. During an input low-to-high transition,
the output transistor Q2 sources large amount of current to
quickly charge up a highly capacitive load which in effect
reduces the bus settling time. This current is specified as
IDYNAMIC.
The negation path is also the Darlington pair consisting of
transistor Q3 and transistor Q4. With M1 connecting to
the input of the Darlington pair, Transistor Q4 then sinks a
large amount of current during the input transition from
high-to-low.
Inverter X2 is a helpful buffer that not only drives the
output toward the upper rail but also pulls the output to
the lower rail.
There are a number of MOSFETs not shown in Figure 11.
These MOSFETs are used to 3-state the buffers. For
instance, R1 and R2 were implemented as resistive
transmission gates to ensure that disabled buffers do not
load the lines of which they are connected.
VCC
R1
Q1
X1
X2
IN
Q2
OUT
R2
M1
Q3
Q4
Figure 11. One Buffer Cell of the ML6516244
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