MAX6469TA33AD3 查看數據表（PDF） - Maxim Integrated
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MAX6469TA33AD3
Maxim Integrated
MAX6469TA33AD3 Datasheet PDF : 20 Pages
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300mA LDO Linear Regulators with Internal
Microprocessor Reset Circuit
MAX6469/MAX6470/MAX6477/MAX6478 Pin Description
PIN
MAX6469/MAX6470
SOT23 TDFN-EP
1
1, 2
2
3
3
4
4
5
5
6
6
7, 8
—
—
BUMP
MAX6477/MAX6478
UCSP
A1
NAME
FUNCTION
IN Regulator Input. Bypass IN to GND with a 0.1µF capacitor.
A2
GND
Ground. This pin also functions as a heatsink. Solder to large pads or
the circuit-board ground plane to maximize thermal dissipation.
A3
SHDN Active-Low Shutdown Input. Connect SHDN to VIN for normal operation.
Active-Low Reset Output. RESET remains low while VOUT is below the
C3
RESET
reset threshold. RESET remains low for the duration of the reset timeout
period after the reset conditions are terminated. RESET is available in
open-drain and push-pull configurations.
Feedback Input for Externally Setting the Output Voltage. Connect SET
C2
SET to GND to select the preset output voltage. Connect SET to an external
resistor-divider network for adjustable output operation.
C1
OUT
Regulator Output. Bypass OUT to GND with a minimum 3.3µF low-ESR
capacitor.
Exposed Paddle (TDFN Only). EP is internally connected to GND.
—
EP
Connect EP to the ground plane to provide a low thermal-resistance
path from the IC junction to the PCB. Do not use as the electrical
connection to GND.
MAX6471/MAX6472/MAX6479/MAX6480 Pin Description
PIN
MAX6471/MAX6472
SOT23 TDFN-EP
1
1, 2
BUMP
MAX6479/MAX6480
UCSP
A1
2
3
A2
3
4
A3
4
5
C3
5
6
C2
6
7, 8
C1
—
—
—
NAME
FUNCTION
IN
GND
MR
RESET
SET
OUT
EP
Regulator Input. Bypass IN to GND with a 0.1µF capacitor.
Ground. This pin also functions as a heatsink. Solder to large pads or
the circuit-board ground plane to maximize thermal dissipation.
Active-Low Manual Reset Input. The reset output is asserted while MR
is pulled low and remains asserted for the duration of the reset timeout
period after MR transitions from low to high. Leave MR unconnected or
connect to VOUT if not used. MR has an internal pullup resistor of 40kΩ
(typ) to VOUT.
Active-Low Reset Output. RESET remains low while VOUT is below the
reset threshold or while MR is held low. RESET remains low for the
duration of the reset timeout period after the reset conditions are
terminated. RESET is available in open-drain and push-pull
configurations.
Feedback Input for Externally Setting the Output Voltage. Connect SET
to GND to select the preset output voltage. Connect SET to an external
resistor-divider network for adjustable output operation.
Regulator Output. Bypass OUT to GND with a minimum 3.3µF low-ESR
capacitor.
Exposed Paddle (TDFN Only). EP is internally connected to GND.
Connect EP to the ground plane to provide a low thermal-resistance
path from the IC junction to the PCB. Do not use as the electrical
connection to GND.
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