APU0066-001QE-TY 查看數據表（PDF） - Anpec Electronics

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APU0066-001QE-TY

16 COM / 40 SEG Driver & Controller for Dot Matrix LCD

Anpec Electronics 

APU0066 PRELIMINARY

ABSOLUTE MAXIMUM RATINGSTA = 25°C

Sym bol

Param eter

R ating

V DD

O perating Voltage

-0.3 ~ +7

V LCD

D river S upply Voltage

VDD - 13.5 ~ VDD + 0.3

V IN

Input Voltage

-0.3 ~ VDD + 0.3

PD

P ower D issipation

500

TOPR

O p e ra tin g Tem p e ra tu re

-20 to +75

TSTG

S to ra g e Tem p e ra tu re R a n g e

-30 to +85

∗ Voltage greater than above may damage to the circuit (VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 )

ELECTRICAL CHARACTERISTICS

U n it

V

V

V

mW

°C

°C

DC Characteristics (VDD = 3V ± 10%, VSS = 0V, TA = -30 ~ 85°C)

S ym b o l

VDD

IDD1

IDD2

V IH1

V IL1

V IH2

V IL2

VOH1

V LH1

VOH2

V LH2

VDCOM

VDSEG

ILKG

Param ete r

Operating Voltage

Operating Current (∗1)

Input Voltage 1

Input Voltage 2

Output Voltage 1

Output Voltage 2

Voltage Drop (∗2)

Input Leakage Current

Test Conditions



Ceram ic Resonator

FOSC = 250KHz

Resistor Oscillation

External Clock Operation

FOSC = 270KHz



High

Low

High



Low

IOH = -0.1 mA

IOL = 0.1mA

IO = -40µA

IO = 40µA

IO = 0.05mA

High

Low

High

Low

COM

SEG

VIN = 0 or VDD

APU0066

Min. Typ. Max.

2.7

3

3.3



0.3

0.5



1.9

-0.3

0.7VDD



2.0



0.8VDD







-1

0.17























0.3

VDD

0.4

VDD

0.2VDD



0.4



0.2VDD

1

1.5

1

IIL

Input Low Current

VDD = 3V (test pull up R)

-10

-50

-120

FEC

Duty

TR

TF

FOSC

VLCD1

V LCD2

External Clock

Internal Clock Frequency (∗3)

LCD Driving Voltage (∗4)

Frequency(∗3)

Duty

Rise Tim e

Fall Tim e

Rf = 75K Ω ± 2%

VDD – V5

1/5 bias

1/4 bias

125

250

350

45

50

55





0.2





0.2

190

270

350

3



10

3



10

Unit

V

mA

V

µA

KHz

%

µs

µs

KHz

V

Applicable

Pin

E, DB0 - DB7

R/W, RS

OSC1

DB0 - DB7

CLK1, CLK2.

M, D

C1 ~ C16

S1 ~ S40

E

RS, R/W,

DB0 - DB7

OSC1

OSC1, OSC2

V1 – V5

Note: ∗1 : The supply current value from VDD when the power condition is as follows

VDD

=

5V,

VSS

=

0V,

V

5

=

-2V

(when

VDD

=

5V)

VDD

=

3V,

VSS

=

0V,

V

5

=

-2V

(when

VDD

=

3V)

∗2

:

The

voltage

drop

from

LCD

bias

terminals

V,

DD

V,

1

V

4

and

V

5

to

each

common

terminal

(C

1

~

C ).

16

And

also

the

voltage

drop

from

LCD

bias

terminals

VDD,

V,

2

V

3

and

V

5

to

each

segment

terminal

(S

1

~

S ).

80

∗3 and ∗4 : Refer to oscillator circuit and input the voltage listed in the table below to V ~ V .

1

5

Copyright  ANPEC Electronics Corp.

3

Rev. A.07 - FEB., 2002

www.anpec.com.tw

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