MAX6900 查看數據表（PDF） - Maxim Integrated
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MAX6900 Datasheet PDF : 17 Pages
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I2C-Compatible RTC in a TDFN
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 1, 6)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Hold Time After (Repeated)
START Condition (After this
Period, the First Clock Is
Generated)
tHD:STA
0.6
µs
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time (Note 7)
Data Setup Time
SCL Low Period
SCL High Period
Minimum SCL/SDA Rise Time
(Note 8)
Maximum SCL/SDA Rise Time
(Note 8)
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tLOW
tHIGH
tr
tr
0.6
µs
0.6
µs
0
0.9
µs
100
ns
1.3
µs
0.6
µs
20 +
ns
0.1CB
300
ns
Minimum SCL/SDA Fall Time
(Receiving) (Notes 8, 9)
tf
Maximum SCL/SDA Fall Time
(Receiving) (Notes 8, 9)
tf
20 +
0.1CB
ns
300
ns
Minimum SDA Fall Time
(Transmitting) (Notes 8, 9)
tf
Maximum SDA Fall Time
(Transmitting) (Notes 8, 9)
tf
Pulse Width of Spike Suppressed
tSP
Capacitive Load for Each
Bus Line
CB
20 +
0.1CB
ns
250
ns
50
ns
400
pF
Note 1: All parameters are 100% tested at TA = +25°C. Limits over temperature are guaranteed by design and not production tested.
Note 2: ICC is specified with SCL = 400kHz and SDA = 400kHz.
Note 3: ITK is specified with SCL = Logic High (4.7kΩ pullup resistor) and SDA = Logic High (4.7kΩ pullup resistor);
I2C-compatible bus inactive.
Note 4: MAX6900 I/O pins do not obstruct the SDA and SCL lines if VCC is switched off.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: All values referred to VIH min and VIL max levels.
Note 7: The MAX6900 internally provides a hold time of at least 300ns for the SDA signal (referred to the VIH min of the SCL signal)
in order to bridge the undefined region of the falling edge of SCL.
Note 8: CB = total capacitance of one bus line in pF.
Note 9: The maximum tf for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tf is
specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tf.
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