MAX6901 查看數據表（PDF） - Maxim Integrated

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MAX6901

3-Wire Serial RTC in a TDFN

Maxim Integrated 

3-Wire Serial RTC in a TDFN

tive alarm function. For example, if the Alarm

Configuration register is set to 0000 0011, ALM OUT is

set when both the minutes and seconds indicated in

the Alarm Threshold registers match the respective

timekeeping registers. Once set, ALM OUT stays high

until it is cleared by reading or writing to the Alarm

Configuration register, or by reading or writing to any of

the Alarm Threshold registers. The Alarm Configuration

register is written with Address/Command 94h, and

read with Address/Command 95h.

Using the On-Board RAM

The static RAM is 31 x 8 bits addressed consecutively

in the RAM address space. Even-addressed com-

mands (C0h–FCh) are used for Writes, and odd-

addressed commands (C1h–FDh) are used for Reads.

The contents of the RAM are static and remain valid for

VCC down to 2V. All RAM data are lost if power is

cycled. The write-protect bit (bit 7 of the Control regis-

ter), when high, disallows any changes to RAM.

3-Wire Serial Interface

Interfacing the MAX6901 with a microcontroller is

accomplished by using a 3-wire, synchronous, serial

interface. Required to communicate are a Chip Select

signal (CS), a Serial Clock signal (SCLK), and a Data

line (I/O).

All data transfers are framed by the CS signal that must

be active-high for any data transfer to occur. At the

beginning of any data transfer (rising edge of CS),

SCLK should be low. This prevents the MAX6901 from

misinterpreting the transition of CS as a high-to-low

transition of SCLK (if SCLK were to be left high when

CS transitions from a low to high). The first 8 bits sent

after CS is pulled high by the microcontroller comprise

the Address/Command Byte, which tells the MAX6901

if the data transfer is a read or a write, and which regis-

ter is read to or written from. Data are clocked into the

MAX6901, through the I/O pin, on the rising edges of

SCLK, and data are clocked out on the falling edge of

SCLK. Data format is always LSB first to MSB last.

When CS is low, I/O is high impedance.

Single data transfer timing is shown in Figure 2. Burst-

mode data transfer timing is shown in Figure 3.

Detailed Read and Write timing diagrams are shown in

Figures 4 and 5, respectively.

Chip Select

CS serves two functions. First, CS turns on the control

logic that allows access to the Shift register for

Address/Command and data transfer. Second, CS pro-

vides a method of terminating either single-byte or mul-

tiple-byte data transfers. All data transfers are initiated

by driving CS high. If CS is low, I/O is high impedance.

At power-up, CS must be low until VCC ≥ 2.0V.

Serial Clock

A clock cycle on SCLK is a rising edge followed by a

falling edge. For data input, data must be valid at I/O

during the rising edge of the clock. For data outputs,

bits are valid on I/O after the falling edge of clock. Also,

SCLK must be low when CS is driven high.

Data Input (Single-Byte Write)

Following the eight SCLK cycles that input a Single-

Byte Write Address/Command, data bits are input on

the rising edges of the next eight SCLK cycles.

Additional SCLK cycles are ignored. Input data LSB first.

Data Input (Burst Write)

Following the eight SCLK cycles that input a Burst Write

Address/Command, data bits are input on the rising

edges of the following SCLK cycles. The number of

clock cycles depends on whether the timekeeping reg-

isters or RAM are being written. A clock Burst Write

requires an Address/Command byte, 7 timekeeping

data bytes, and 1 Control register byte. A Burst Write to

RAM may be terminated after any complete data byte

by driving CS low. Input data LSB first (Figures 3 and 5).

Data Output (Single-Byte Read

and Burst Read)

A read from the MAX6901 is initiated by an Address/

Command Write from the microcontroller (master) to the

MAX6901 (slave). The Address/Command Write portion

of the data transfer is clocked into the MAX6901 on ris-

ing clock edges. On the eighth rising SCLK edge, the

last bit of the Address/Command Byte is clocked into

the MAX6901. After t CDH (CLK to Data Hold time,

Figure 4), the microcontroller must release the data

line. On the eighth falling edge of SCLK, the MAX6901

takes control of the data line and begins to output data.

The MAX6901 outputs data on the falling edge of SCLK

after t CDD (CLK to Data Delay time, Figure 4). On the

next rising edge of SCLK, I/O goes to high impedance

after t CCZ (which is specified with a maximum time).

Minimum time for t CCZ can be 0ns. Since the I/O line

can go to high impedance on the rising edge of SCLK,

it is best to read the data from the MAX6901 before the

rising edge of SCLK but after t CDD (CLK to Data Delay

time). This is best accomplished through the microcon-

troller I/O port pins by writing a low to SCLK, waiting

tCDD (CLK to Data Delay time), reading the MAX6901

I/O pin, and then writing a high to SCLK. Data bytes are

output LSB first. Additional SCLK cycles transmit addi-

tional data bits, as long as CS remains high. This per-

mits continuous burst-mode read capability.

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