MAX7000A 查看數據表（PDF） - Altera Corporation
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MAX7000A Datasheet PDF : 64 Pages
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MAX 7000A Programmable Logic Device Data Sheet
Table 1. MAX 7000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
tPD (ns)
tSU (ns)
tFSU (ns)
tCO1 (ns)
fCNT (MHz)
EPM7032AE
600
32
2
36
4.5
2.9
2.5
3.0
227.3
EPM7064AE
1,250
64
4
68
4.5
2.8
2.5
3.1
222.2
EPM7128AE
2,500
128
8
100
5.0
3.3
2.5
3.4
192.3
EPM7256AE
5,000
256
16
164
5.5
3.9
2.5
3.5
172.4
EPM7512AE
10,000
512
32
212
7.5
5.6
3.0
4.7
116.3
...and More
Features
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
■ Programmable power-up states for macrocell registers in
MAX 7000AE devices
■ Programmable power-saving mode for 50% or greater power
reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins
2
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