MAX6972 查看數據表（PDF） - Maxim Integrated

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MAX6972

16-Output PWM LED Drivers for Message Boards

Maxim Integrated 

16-Output PWM LED Drivers

for Message Boards

HOST

CLKO

DOUT

LOADO

LOADI

DIN

CLKI

CLK0

D0

LOAD0

MAX6972/MAX6973

1

CLKI

CLKO

DIN

LOADI

DOUT

LOADO

CLK1

D1

LOAD1

MAX6972/MAX6973

2

CLKI

CLKO

DIN

LOADI

DOUT

LOADO

CLK2

D2

LOAD2

MAX6972/MAX6973

3

CLKI

CLKO

DIN

LOADI

DOUT

LOADO

CLK3

D3

LOAD3

Figure 8. Example Showing Three-Device Cascade Connection Scheme with the Interconnecting Nodes Labeled for Clarity

1

LOADI 0

DATA: CALDAC DATA 1

Z CALDAC

Y CALDAC

DATA: CALDAC DATA 2

Z CALDAC

Y CALDAC

DATA: CALDAC DATA 3

Z CALDAC

Y CALDAC

DIN

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

CLKI

(CONTINUOUS) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Figure 9. Timing Example Showing CALDAC Data Set for Three Cascaded Devices

Serial-Interface Cascade Timing

The MAX6972/MAX6973 serial-interface protocol timing

is simplified by the guaranteed setup and hold charac-

teristics of the outputs from one device driving the

inputs of another. An example of a cascade of three

MAX6972/MAX6973 devices is shown in Figure 8.

Example of Serial-Interface

Cascade Timing

The basic timing of a MAX6972/MAX6973 cascaded

chain of three devices demonstrates the principle that

applies to any number of cascaded devices. The first

device connected to the host transmitter is referenced

as 1, and the remaining devices are referenced as 2

and 3. Device 3 outputs connect to the host for commu-

nicating diagnostic and fault counter data.

The first MAX6972/MAX6973, device 1, receives the

header and captures the first set of data bits. The

number of captured bits is determined by the command

given in the header. A timing example of the data trans-

fer for the Load CALDAC command is shown in Figure

9. Device 1 does not send the captured data out on

DOUT. Instead, device 1 sends out a new header 17

clock cycles after the reception of the first header bit on

DIN. The data flow on each interconnect node is shown

in Figure 10.

CLK0

D0

HEADER 1

WORD 1

WORD 2

WORD 3 T

17 CLOCKS

D1

HEADER 2

WORD 2

WORD 3 T

17 CLOCKS

D2

HEADER 3

WORD 3 T

17 CLOCKS

D3

HEADER 4

T

Figure 10. Data Cascading Example for 16-Bit Data Words

After capturing the first data set, device 1 transmits all

following data segments and the optional tail segment

on DOUT, delayed by one CLKI cycle. Device 2

receives the new header from device 1, followed by

data that now begins with device 2’s data set. Device 2

repeats the same process as described above; captur-

ing the first data set received, appending a new head-

er, and passing all subsequent data out DOUT to the

next device 3. Device 3 captures the last data set and

transmits a header followed by the tail segment. The

last header and tail segments are clocked back into the

host receiver. The header received by the host contains

the updated fault counter data. The tail data bit pattern

can be compared to the tail data originally transmitted

by the host for data integrity check.

When the MAX6972/MAX6973 send individual-intensity

PWM data, the data segment bit length is large due to

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