MAX6946CAWE 查看數據表（PDF） - Maxim Integrated

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MAX6946CAWE

10-Port, Constant-Current LED Driver and I/O Expander with PWM Intensity Control

Maxim Integrated 

10-Port, Constant-Current LED Driver and

I/O Expander with PWM Intensity Control

TIMING CHARACTERISTICS (Figure 8)

(VDD = 2.25V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.) (Note 1)

PARAMETER

Internal PWM Clock Frequency

External PWM Clock Frequency

Serial-Clock Frequency

Bus Free Time Between a STOP and

a START Condition

SYMBOL

CONDITIONS

16-pin TQFN

fINT

16-bump WLP

fOSC

fSCL

tBUF

MIN TYP MAX UNITS

23

32

42

kHz

20

32

45

100 kHz

400 kHz

1.3

µs

Hold Time, (Repeated) START

Condition

tHD, STA

0.6

µs

Repeated START Condition Setup

Time

STOP Condition Setup Time

Data Hold Time

Data Setup Time

SCL Clock Low Period

SCL Clock High Period

Rise Time of Both SDA and SCL

Signals, Receiving

Fall Time of Both SDA and SCL

Signals, Receiving

Fall Time of SDA Transmitting

Pulse Width of Spike Supressed

Capacitive Load for Each Bus Line

RST Pulse Width

RST Rising Edge to

MAX6946/MAX6947 ACK to Cancel

Reset Run

tSU, STA

tSU, STO

tHD, DAT

tSU, DAT

tLOW

tHIGH

(Note 3)

tR

(Notes 4, 5)

tF

(Notes 4, 5)

tF, TX (Notes 4, 6)

tSP

Cb

tW

tRSTRUN

(Note 7)

(Note 4)

Reset Run enabled,

internal oscillator

enabled

16-pin TQFN

16-bump WLP

0.6

µs

0.6

µs

0.9

µs

180

ns

1.3

µs

0.7

µs

20

+ 0.1Cb

300

ns

20

300

ns

+ 0.1Cb

20

+ 0.1Cb

250

ns

50

ns

400

pF

0.1

µs

3.0

ms

2.5

RST Rising Edge to

MAX6946/MAX6947 ACK to Ensure

Reset Run

tRSTRUN

Reset Run enabled, internal oscillator

enabled

5.6

ms

Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.

Note 2: Port current is factory trimmed to meet a median sink current of 20mA and 10mA over all ports. The ΔIOUT specification

guarantees current matching between parts.

Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to

bridge the undefined region of SCL’s falling edge.

Note 4: Not production tested. Guaranteed by design.

Note 5: Cb = total capacitance of one bus line in picoFarads; tR and tF are measured between 0.3 x VDD and 0.7 x VDD.

Note 6: ISINK ≤ 6mA.

Note 7: Guaranteed by design. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50ns.

4 _______________________________________________________________________________________

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