MAX8775 查看數據表（PDF） - Maxim Integrated

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MAX8775

Dual and Combinable Graphics Core Controller for Notebook Computers

Maxim Integrated 

Dual and Combinable Graphics Core

Controller for Notebook Computers

Pin Description

PIN NAME

FUNCTION

SMPS1 Overvoltage Adjust Input. The overvoltage trip threshold for SMPS1 is 200mV above the voltage at OVP1.

1

OVP1 Connect OVP1 to VCC to disable OVP for SMPS1.

OVP1 sets the overvoltage threshold for both phases in combined mode.

Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and AGND to set the switching frequency

(per phase):

2

OSC

fOSC = 300kHz x 143kΩ / ROSC

A 71.5kΩ to 432kΩ corresponds to switching frequencies of 600kHz to 100kHz, respectively.

Ensure the minimum on-time requirement is met for the selected frequency.

3

REFIN1

SMPS1 External Reference Input. REFIN1 sets the output regulation voltage (VCSL1 = VREFIN1).

REFIN1 sets the output regulation voltage in combined mode (VCSL1 = VCSL2 = VREFIN1).

4

VCC

Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 10Ω resistor.

Bypass VCC to AGND with a 1µF or greater ceramic capacitor.

5 AGND Analog Ground. Connect backside pad to AGND.

2.5V Reference Voltage Output. Bypass REF to AGND with a 0.1µF or greater ceramic capacitor. The maximum

6

REF

value of this cap is 1µF. The reference can source up to 250µA. Loading REF degrades output-voltage accuracy

according to the REF load-regulation error (see Typical Operating Characteristics). The reference shuts down

when both ON1 and ON2 are low.

7

REFIN2

SMPS2 External Reference Input. REFIN2 sets the feedback regulation voltage (VCSL2 = VREFIN2).

Connect REFIN2 to VCC to select combined mode. See OVP2 pin connection below.

SMPS2 Overvoltage Adjust Input. The overvoltage trip threshold for SMPS2 is 200mV above the voltage at OVP2.

8

OVP2

Connect OVP2 to VCC to disable OVP for SMPS2.

Connect OVP2 to REF in combined mode when OVP is enabled.

Connect OVP2 to VCC in combined mode when OVP is disabled.

SMPS2 Slew-Rate Control. Connect a capacitor from SLEW2 to AGND to set the SMPS2 slew rate:

9 SLEW2

Slew Rate (ΔVOUT2 / Δt) = ISLEW2 / CSLEW2

During startup and shutdown, SMPS2 ramps at 1/5 the programmed slew rate.

Connect SLEW2 to SLEW1 in combined mode.

Current-Balance Compensation for SMPS2. When combining SMPS1 and SMP2, connect a 47pF capacitor

10 CCI2 between CCI2 and AGND.

Leave CCI2 open when operating SMPS1 and SMPS2 separately.

SMPS2 Open-Drain Power-Good Output. PGOOD2 is low when SMPS2 is more than 150mV below its regulation

11 PGOOD2 threshold, when a 0V fault occurs, during soft-start, and in shutdown.

PGOOD2 is the current-balance fault indicator when operating in combined mode.

Low-Noise Mode Control for SMPS2. Connect SKIP2 to GND for normal Idle Mode (pulse-skipping) operation or

12 SKIP2 to VCC for PWM mode (fixed frequency).

SKIP2 is ignored in combined mode.

13

CSH2 Positive Current-Sense Input for SMPS2. Connect to the positive terminal of the current-sense element. Figure 10

describes two different current-sensing options.

Negative Current-Sense and Feedback Input for SMPS2. Connect to the negative terminal of the current-sense

14 CSL2 element. CSL2 regulates to REFIN2. Figure 10 describes two different current-sensing options.

CSL2 regulates to REFIN1 in combined mode.

SMPS2 Enable Input. Drive ON2 high to enable SMPS2. Drive ON2 low to shut down SMPS2.

15

ON2 When both outputs are combined, ON1 is the master control input to enable/disable the combined output, while

ON2 enables/disables phase 2, allowing 1- or 2-phase operation.

10 ______________________________________________________________________________________

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