MC68020 查看數據表（PDF） - Freescale Semiconductor

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MC68020

MICROPROCESSORS USER’S MANUAL

Freescale Semiconductor 

Freescale Semiconductor, Inc.

The SR (see Figure 1-4) stores the processor status. It contains the condition codes that

reflect the results of a previous operation and can be used for conditional instruction

execution in a program. The condition codes are extend (X), negative (N), zero (Z),

overflow (V), and carry (C). The user byte, which contains the condition codes, is the only

portion of the SR information available in the user privilege level, and it is referenced as

the CCR in user programs. In the supervisor privilege level, software can access the entire

SR, including the interrupt priority mask (three bits) and control bits that indicate whether

the processor is in:

1. One of two trace modes (T1, T0)

2. Supervisor or user privilege level (S)

3. Master or interrupt mode (M)

SYSTEM BYTE

USER BYTE

(CONDITION CODE REGISTER)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T1 T0 S M 0 I2 I1 I0 0 0 0 X N Z V C

TRACE

ENABLE

INTERRUPT

PRIORITY MASK

SUPERVISOR/USER LEVEL

MASTER/INTERRUPT MODE

Figure 1-4. Status Register (SR)

CARRY

OVERFLOW

ZERO

NEGATIVE

EXTEND

The VBR contains the base address of the exception vector table in memory. The

displacement of an exception vector is added to the value in this register to access the

vector table.

The alternate function code registers, SFC and DFC, contain 3-bit function codes. For the

MC68020, function codes can be considered extensions of the 32-bit linear address that

optionally provide as many as eight 4-Gbyte address spaces; for the MC68EC020,

function codes can be considered extensions of the 24-bit linear address that optionally

provide as many as eight 16-Mbyte address spaces. Function codes are automatically

generated by the processor to select address spaces for data and program at the user

and supervisor privilege levels and to select a CPU address space for processor functions

(e.g., coprocessor communications). Registers SFC and DFC are used by certain

instructions to explicitly specify the function codes for operations.

The CACR controls the on-chip instruction cache of the MC68020/EC020. The CAAR

stores an address for cache control functions.

MOTOROLA

M68020 USER’S MANUAL

1-7

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