MC68020 查看數據表（PDF） - Freescale Semiconductor

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MC68020

MICROPROCESSORS USER’S MANUAL

Freescale Semiconductor 

Freescale Semiconductor, Inc.

SEQUENCER

CONTROL

UNIT

STAGE

D

INSTRUCTION PIPE

STAGE

C

STAGE

B

CACHE

HOLDING

REGISTER

INSTRUCTION

FLOW FROM

CACHE AND

MEMORY

EXECUTION

UNIT

Figure 1-5. Instruction Pipe

The sequencer is either executing microinstructions or awaiting completion of accesses

that are necessary to continue executing microcode. The bus controller is responsible for

all bus activity. The sequencer controls the bus controller, instruction execution, and

internal processor operations such as the calculation of effective addresses and the

setting of condition codes. The sequencer initiates instruction word prefetches and

controls the validation of instruction words in the instruction pipe.

Prefetch requests are simultaneously submitted to the cache holding register, the

instruction cache, and the bus controller. Thus, even if the instruction cache is disabled,

an instruction prefetch may hit in the cache holding register and cause an external bus

cycle to be aborted.

1.7 CACHE MEMORY

Due to locality of reference, instructions that are used in a program have a high probability

of being reused within a short time. Additionally, instructions that reside in proximity to the

instructions currently in use also have a high probability of being utilized within a short

period. To exploit these locality characteristics, the MC68020/EC020 contains an on-chip

instruction cache.

The cache improves the overall performance of the system by reducing the number of bus

cycles required by the processor to fetch information from memory and by increasing the

bus bandwidth available for other bus masters in the system.

MOTOROLA

M68020 USER’S MANUAL

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