MT28F016S5VG-9 查看數據表（PDF） - Micron Technology
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MT28F016S5VG-9 Datasheet PDF : 24 Pages
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ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
MEMORY ARCHITECTURE
The MT28F016S5 memory array architecture is de-
signed to allow sectors to be erased without disturbing
the rest of the array. The array is divided into 32
addressable blocks that are independently erasable.
When blocks rather than the entire array are erased, the
total device endurance is enhanced, as is system flex-
ibility. Only the ERASE functions are block-oriented.
All READ and WRITE operations are done on a random-
access basis. Figure 1 illustrates the memory address
map.
OUTPUT (READ) OPERATIONS
The MT28F016S5 features three different types of
READs. Depending on the current mode of the device,
a READ operation will produce data from the memory
array, status register or one of the device configuration
registers. In each of these three cases, the WE#, CE# and
OE# inputs are controlled in a similar manner. Moving
between modes to perform a specific READ will be
covered in the Command Execution section.
MEMORY ARRAY
To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data will be output
on the DQ pins once these conditions have been met
and a valid address is given. Valid data will remain on
the DQ pins until the address changes, or until OE# or
0
64KB
64KB
16Mb
31
64KB
Figure 1
Memory Address Map
CE# goes HIGH, whichever occurs first. The DQ pins
will continue to output new data after each address
transition as long as OE# and CE# remain LOW.
After power-up or RESET, the device will automati-
cally be in the array read mode. All commands and their
operations are covered in the Command Set and Com-
mand Execution sections.
STATUS REGISTER
Performing a READ of the status register requires the
same input sequencing as a READ of the array except
that the address inputs are “Don’t Care.” Data from the
status register is latched on the falling edge of OE# or
CE#, whichever occurs last. If the contents of the status
register change during a READ of the status register,
either OE# or CE# may be toggled while the other is
held LOW to update the output.
Following a WRITE or ERASE operation, the device
automatically enters the status register read mode. In
addition, a READ during a WRITE or ERASE operation
will produce the status register contents on DQ0-DQ7.
When the device is in ERASE SUSPEND mode, a READ
operation will produce the status register contents until
another command is issued. While the device is in
certain other modes, READ STATUS REGISTER may be
given to return to the status register read mode. All
commands and their operations are covered in the
Command Set and Command Execution sections.
DEVICE CONFIGURATION REGISTERS
Reading any of the device configuration registers
requires the same input sequencing as reading the
status register except that specific addresses must be
issued. WE# must be HIGH, and OE# and CE# must be
LOW. To read the manufacturer compatibility ID, ad-
dresses must be at 000000H, and to read the device ID,
addresses must be at 000001H.
While the device is in certain other modes, READ
DEVICE CONFIGURATION may be given to return to
the configuration registers read mode. All commands
and their operations are covered in the Command Set
and Command Execution sections.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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