MT47H128 查看數據表（PDF） - Micron Technology

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MT47H128

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

Functional Block Diagrams

The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-

nally configured as a multibank DRAM.

Figure 3: 256 Meg x 4 Functional Block Diagram

ODT

CKE

CK

CK#

CS#

RAS#

CAS#

WE#

Control

logic

Mode

registers

17

A0–A13,

BA0–BA2

17

Address

register

Refresh

counter

14

14

3

11

14

Row-

address

MUX

Bank 7

Bank 7

Bank 6

Bank 6

Bank 5

Bank 5

Bank 4

Bank 4

Bank 3

Bank 3

Bank 2

Bank 2

Bank 1

Bank 1

Bank 0

Bank 0

row-

address

latch

16,384

Memory array

(16,384 x 512 x 16)

and

decoder

Sense amplifiers

8,192

16

2

Bank

control

logic

I/O gating

DM mask logic

512

(x16)

COL0, COL1

CK, CK#

4

16 Read

latch

4

4

4

4

MUX DATA

DLL

DRVRS

DQS

2

generator DQS, DQS#

Input

registers

1

1

WRITE

FIFO

16

and

drivers

1

41

Mask 1

4

1

11

1

RCVRS

4

Column- 9

address

counter/

2

latch

Column

decoder

CK, CK#

CK out 16 4

CK in Data 4

4

COL0, COL1

44

4

4

2

ODT control

sw1 sw2 sw3

VDDQ

sw1 sw2 sw3

R1 R2 R3

R1 R2 R3

DQ0–DQ3

sw1 sw2 sw3

R1 R2 R3

R1 R2 R3

DQS, DQS#

sw1 sw2 sw3

R1 R2 R3

R1 R2 R3

DM

VSSQ

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

11

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

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