MT58L1MY18D 查看數據表（PDF） - Micron Technology
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MT58L1MY18D Datasheet PDF : 34 Pages
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20
SA0, SA1, SAs
MODE
ADV#
CLK
ADSC#
ADSP#
BWb#
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
ADDRESS
REGISTER
20
18
20
2 SA0-SA1
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA1'
SA0'
BYTE “b”
WRITE REGISTER
BYTE “a”
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
9
BYTE “b”
9
9
WRITE DRIVER
BYTE “a”
9
1 Meg x 9 x 2
MEMORY 18
ARRAY
SENSE
AMPS
18
OUTPUT 18
REGISTERS
OUTPUT
BUFFERS
E
18
WRITE DRIVER
DQs
DQPa
DQPb
INPUT
18
REGISTERS
2
19
SA0, SA1, SAs
MODE
ADV#
CLK
ADSC#
ADSP#
BWd#
BWc#
BWb#
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
ADDRESS 19
17
19
REGISTER
SA0-SA1
SA1'
Q1
BINARY
COUNTER SA0'
CLR
Q0
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
BYTE “b”
WRITE REGISTER
BYTE “a”
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
BYTE “d”
9 WRITE DRIVER 9
9
BYTE “c”
WRITE DRIVER
9
512K x 8 x 4
(x32)
512K x 9 x 4
(x36)
36
SENSE 36
AMPS
OUTPUT
REGISTERS 36
OUTPUT
BUFFERS
36
BYTE “b”
9 WRITE DRIVER 9
MEMORY
ARRAY
E
BYTE “a”
9 WRITE DRIVER 9
DQs
DQPa
DQPb
DQPc
DQPd
INPUT
36
REGISTERS
4
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for
detailed information.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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