MT58L1MY18D 查看數據表（PDF） - Micron Technology
零件编号
产品描述 (功能)
生产厂家
MT58L1MY18D Datasheet PDF : 34 Pages
| |||
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can be
from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device,
BWa# controls DQas and DQPa; BWb# controls DQbs
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQas and DQPa; BWb# controls
DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. GW# LOW causes all bytes to
be written. Parity bits are only available on the x18 and
x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing
system performance.
Micron’s 16Mb SyncBurst SRAMs operate from a
+3.3V or +2.5V power supply, and all inputs and outputs
are TTL-compatible. Users can implement either a 3.3V
or 2.5V I/O for the +3.3V VDD or a 2.5V I/O for the +2.5V
VDD. The device is ideally suited for Pentium® and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please refer to the Micron Web site
(www.micronsemi.com/en/products/sram/) for the lat-
est data sheet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
x32/x36
NC NC/DQPc1
NC
DQc
NC
DQc
VDDQ
VSS
NC
DQc
NC
DQc
DQb
DQc
DQb
DQc
VSS
VDDQ
DQb
DQc
DQb
DQc
NC
VDD
NC
VSS
DQb
DQd
DQb
DQd
VDDQ
VSS
DQb
DQd
DQb
DQd
DQPb
DQd
NC
DQd
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
VSS
VDDQ
NC
DQd
NC
DQd
NC NC/DQPd1
MODE (LBO#)
SA
SA
SA
SA
SA1
SA0
DNU
DNU
VSS
VDD
SA
SA
SA
SA
SA
SA
SA
SA
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
x32/x36
NC NC/DQPa1
NC
DQa
NC
DQa
VDDQ
VSS
NC
DQa
NC
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
DQa
DQb
DQa
DQb
VDDQ
VSS
DQa
DQb
DQa
DQb
DQPa
DQb
NC
DQb
NOTE: 1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
VSS
VDDQ
NC
DQb
NC
DQb
SA NC/DQPb1
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
VSS
VDD
CE2#
BWa#
BWb#
NC
BWc#
NC
BWd#
CE2
CE#
SA
SA
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
Share Link: 