MT58L1MY18D 查看數據表（PDF） - Micron Technology
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MT58L1MY18D Datasheet PDF : 34 Pages
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ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
x32/x36 SYMBOL TYPE
DESCRIPTION
84
84
ADSP# Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
85
85
ADSC# Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
31
MODE Input Mode: This input selects the burst sequence. A LOW on this pin
(LBO#)
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating. LBO# is
the JEDEC-standard term for MODE.
(a) 58, 59, (a) 52, 53,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b) 8, 9, 12, (b) 68, 69
13, 18, 19, 22, 72-75, 78, 79
23
(c) 2, 3, 6-9,
12, 13
(d) 18, 19,
22-25, 28, 29
DQa
DQb
DQc
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and
x36 versions, Byte “a” is associated with DQa pins; Byte “b” is
associated with DQb pins; Byte “c” is associated with DQc pins;
Byte “d” is associated with DQd pins. Input data must meet setup
and hold times around the rising edge of CLK.
DQd
74
51
NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these pins are No
24
80
NC/DQPb I/O Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte
–
1
NC/DQPc
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
–
30
NC/DQPd
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is
DQPd.
15, 41, 65,
91
15, 41, 65,
91
VDD Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27, VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
54, 61, 70, 77 54, 61, 70, 77
Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21, VSS Supply Ground: GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39
38, 39
DNU
– Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7, 14 14, 16, 66
NC
16, 25, 28-30,
51-53, 56, 57,
66, 75, 78, 79,
95, 96
– No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
NA
NA
NF
– No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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