5962-8959817MTA 查看數據表（PDF） - Austin Semiconductor

零件编号

产品描述 (功能)

生产厂家

5962-8959817MTA

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

Austin Semiconductor 

Austin Semiconductor, Inc.

SRAM

MT5C1008

AC TEST CONDITIONS

Input pulse levels ................................... Vss to 3.0V

Input rise and fall times ....................................... 5ns

Input timing reference levels ............................. 1.5V

Output reference levels ..................................... 1.5V

Output load .............................. See Figures 1 and 2

Q

255

+5V

480

Q

30

255

+5V

480

5 pF

Fig. 1 Output Load

Equivalent

Fig. 2 Output Load

Equivalent

NOTES

1. All voltages referenced to VSS (GND).

2. -2V for pulse width < 20ns

3. ICC is dependent on output loading and cycle rates.

The specified value applies with the outputs

unloaded, and f = 1 Hz.

tRC (MIN)

4. This parameter is guaranteed but not tested.

5. Test conditions as specified with the output loading

as shown in Fig. 1 unless otherwise noted.

6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE

are specified with CL = 5pF as in Fig. 2. Transition is

measured ±200mV typical from steady state voltage,

allowing for actual tester RC time constant.

7. At any given temperature and voltage condition,

tHZCE is less than tLZCE, and tHZWE is less than

tLZWE and tHZOE is less than tLZOE.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip enables and

output enables are held in their active state.

10. Address valid prior to, or coincident with, latest

occurring chip enable.

11. tRC = Read Cycle Time.

12. CE2 timing is the same as CE1\ timing. The

waveform is inverted.

13. Chip enable (CE1\, CE2) and write enable (WE\) can

initiate and terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTION

VCC for Retention Data

CONDITIONS

SYMBOL MIN

VDR

2

MAX

---

CE\ > (VCC - 0.2V)

Data Retention Current

VIN > (VCC - 0.2V) VCC = 2V ICCDR

1.0

or < 0.2V, f=0

Chip Deselect to Data

Retention Time

Operation Recovery Time

tCDR

0

---

tR

tRC

UNITS NOTES

V

mA

ns

4

ns

4, 11

LOW Vcc DATA RETENTION WAVEFORM

MT5C1008

Rev. 6.5 7/02

VCC

CE1\

CE2

tCDR

VIH

VIL

111122223333444455556666777788889999

VIH

VIL

111122223333444455556666777788889999

DATA RETENTION MODE

4.5V

VDR > 2V

4.5V

tR

VDR

<VSS + 0.2V

111122223333444455556666111177772111122288883222233343343344

111122223333444455556666111177772111122288883222233343343344

111122223333DON’T CARE

1111222233334444UNDEFINED

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

Share Link: