OR2C04A 查看數據表（PDF） - Lattice Semiconductor
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OR2C04A Datasheet PDF : 192 Pages
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Data Sheet
January 2002
ORCA Series 2 FPGAs
FPGA States of Operation (continued)
DONE
I/O
ATT3000
F
CCLK PERIOD
GLOBAL
RESET
DONE
I/O
GSRN
ACTIVE
ORCA CCLK_NOSYNC
F
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
ORCA CCLK_SYNC
DONE IN
DONE
C1, C2, C3, OR C4
I/O
Di Di + 1
Di + 2
Di + 3
GSRN
ACTIVE
Di Di + 1
Di + 2
Di + 3
F
Di + 4
Di + 4
UCLK
DONE
I/O
GSRN
ACTIVE
ORCA UCLK_NOSYNC
F
C1 U1
U2
U3
U4
U1
U2
U3
U4
U1
U2
U3
U4
ORCA UCLK_SYNC
Partial Reconfiguration
All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
Other Configuration Options
Configuration options used during device start-up were
previously discussed in the FPGA States of Operation
section of this data sheet. There are many other config-
uration options available to the user that can be set
during bit stream generation in ORCA Foundry. These
include options to enable boundary scan, readback
options, and options to control and use the internal
oscillator after configuration.
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ORCA Foundry documenta-
tion.
DONE IN
DONE
C1 U1, U2, U3, OR U4
F
I/O
Di Di + 1 Di + 2 Di + 3 Di + 4
GSRN
ACTIVE
Di Di + 1 Di + 2 Di + 3
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
F = finished, no more CLKs required.
5-2761(F).r4
Figure 38. Start-Up Waveforms
Configuration Data Format
The ORCA Foundry Development System interfaces
with front-end design entry tools and provides the tools
to produce a fully configured FPGA. This section dis-
cusses using the ORCA Foundry Development System
to generate configuration RAM data and then provides
the details of the configuration frame format.
The ORCA Series 2 series of FPGAs are enhanced
versions of the ORCA ATT2Cxx/ATT2Txx architectures
that provide upward bit stream compatibility for both
series of devices as well as with each other.
Lattice Semiconductor
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