OR4E10 查看數據表（PDF） - Agere -> LSI Corporation
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OR4E10 Datasheet PDF : 124 Pages
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Preliminary Data Sheet
December 2000
ORCA Series 4 FPGAs
Embedded Block RAM
The ORCA Series 4 devices complement the distrib-
uted PFU RAM with large blocks of memory macro-
cells. The memory is available in 512 words by 18 bits/
word blocks with two write and two read ports. Two byte
lane enables also operate with quad-port functionality.
Additional logic has been incorporated for FIFO, multi-
plier, and CAM implementations. The RAM blocks are
organized along the PLC rows and are added in pro-
portion to the FPGA array sizes as shown in Table 8.
The contents of the RAM blocks may be optionally ini-
tialized during FPGA configuration.
Table 8. ORCA Series 4— Available Embedded
Block RAM
Device
OR4E2
OR4E4
OR4E6
OR4E10
OR4E14
Number of
Blocks
8
12
16
20
24
Number of
EBR Bits
74K
111K
148K
185K
222K
Each highly flexible 512 x 18 (quad-port, two read/two
write) RAM block can be programmed by the user to
meet their particular function. Each of the EBR configu-
rations use the physical signals as shown in
Table 9. Quad-port addressing permits simultaneous
read and write operations.
The EBR ports are written synchronously on the posi-
tive edge of CKW. Synchronous read operations use
the positive edge of CKR. Options are available to use
synchronous read address registers and read output
registers, or to bypass these registers and have the
RAM read operate asynchronously.
EBR Features
Quad-Port Modes (Two Read/Two Write)
s 512 x 18 with optional built-in arbitration between
write ports.
s 1024 x 18 built on two blocks with built-in decode
logic for simplified implementation and increased
speed.
Dual-Port Modes (One Read/One Write)
s One 256 x 36.
s One 1K x 9.
s Two 512 x 9 built in one EBR with two separate read,
write clocks and enables for independent operation.
s Two RAMs with a user customized number of words
whose sum is 512 (or less) by 18.
The joining of RAM blocks is supported to create wider
and deeper memories. The adjacent routing interface
provided by the CIBs allow the cascading of blocks
together with minimal penalties due to routing delays.
FIFO Modes
FIFOs can be configured to 256, 512, or 1K depths and
36, 18, or 9 widths respectively or two-512 x 9 but also
can be expanded using multiple blocks. FIFO works
synchronously with the same read and write clock
where the read port can be registered on the output or
not registered. It can also be optionally configured
asynchronously with different read and write clocks.
Integrated flags allow the user the ability to fully utilize
the EBR for FIFO, without the need to dedicate an
address for providing distinct full/empty status. There
are four programmable flags provided for each FIFO:
Empty, partially empty, full, and partially full FIFO sta-
tus. The partially empty and partially full flags are pro-
grammable with the flexibility to program the flags to
any value from the full or empty threshold. The pro-
grammed values can be set to a fixed value through the
bit stream, or a dynamic value can be controlled by
input pins of the EBR FIFO.
Multiplier Modes
The ORCA EBR supports two variations of multiplier
functions. Constant coefficient MULTIPLY [KCM] mode
will produce a 24-bit output of a fixed 8-bit constant
multiply of a 16-bit number or a fixed 16-bit constant
multiply of an 8-bit number. This KCM multiplies a con-
stant times a 16- or 8-bit number and produces a prod-
uct as a 24-bit result. The coefficient and multiplication
tables are stored in memory. Both the input and outputs
can be configured to be registered for pipelining. Both
write ports are available during MULTIPLY mode so
that the user logic can update and modify the coeffi-
cients for dynamic coefficient updates.
An 8 x 8 MULTIPLY mode is configurable to either a
pipelined or combinatorial multiplier function of two
8-bit numbers. Two 8-bit operands are multiplied to
yield a 16-bit product. The input and outputs can be
registered in pipeline mode.
Lucent Technologies Inc.
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