PCF8563 查看數據表（PDF） - Philips Electronics
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PCF8563 Datasheet PDF : 30 Pages
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Philips Semiconductors
PCF8563
Real-time clock/calendar
Table 5: BCD formatted registers overview
Bit positions labelled as ‘−’are not implemented.
Address Register name BCD format tens nibble
Bit 7
Bit 6
Bit 5
23
22
21
02H
Seconds
VL
03H
Minutes
−
04H
Hours
−
−
05H
Days
−
−
06H
Weekdays
−
−
−
07H
Months/Century C
−
−
08H
Years
09H
Minute alarm
AE
0AH
Hour alarm
AE
−
0BH
Day alarm
AE
−
0CH
Weekday alarm AE
−
−
BCD format units nibble
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
23
22
21
20
<seconds 00 to 59 coded in BCD>
<minutes 00 to 59 coded in BCD>
<hours 00 to 23 coded in BCD>
<days 01 to 31 coded in BCD>
−
−
<weekdays 0 to 6 > [1]
<months 01 to 12 coded in BCD>
<years 00 to 99 coded in BCD>
<minute alarm 00 to 59 coded in BCD>
<hour alarm 00 to 23 coded in BCD>
<day alarm 01 to 31 coded in BCD>
−
−
<weekday alarm 0 to 6 > [1]
[1] Not coded in BCD.
8.6.1 Control/Status 1 register
Table 6: Control/Status 1 register bits description (address 00H)
Bit
Symbol Description
7
TEST1 TEST1 = 0; normal mode.
TEST1 = 1; EXT_CLK test mode; see Section 8.7.
5
STOP STOP = 0; RTC source clock runs.
STOP = 1; all RTC divider chain flip-flops are asynchronously set
to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still
available).
3
TESTC TESTC = 0; power-on reset override facility is disabled (set to logic 0
for normal operation).
TESTC = 1; power-on reset override is enabled.
6, 4, 2 to 0 0
By default set to logic 0.
9397 750 04855
Product specification
16 April 1999
© Philips Electronics N.V. 1999. All rights reserved.
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