R8A20210BG 查看數據表（PDF） - Renesas Electronics

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R8A20210BG

Network Address Search Engine (9 M/18 M-bit Full Ternary CAM)

Renesas Electronics 

R8A20211BG/R8A20210BG (MARIE_Blade)

• JTAG Interface: 5 pins

Pin Name

Symbol

I/O

Function

Test mode select

TMS

I Gives input command for TAP controller.

Test data input

TDI

I Serial input of registers placed between TDI and TDO.

Test data output

TDO

O Serial output of registers placed between TDI and TDO. This output is

active depending on the state of the TAP controller.

Test clock

TCK

I Clock input of TAP controller. Each TAP event is clocked. Test inputs

are captured on rising edge of TCK, while test outputs are driven from

the falling edge of TCK.

JTAG reset

TRST

I JTAG reset can be used to reset TAP controller.

Note: JTAG specification is referenced to IEEE 1149.1.

• Power and Ground

Pin Name

Symbol

Vectored

V_CORE

Voltage for search V_MAT

I/O buffer

VCCQ

supply voltage

Input reference

V_REF

voltage

Ground

GND

Supply voltage for VPLL

PLL

Ground for PLL

GPLL

Pins

50

41

24

Function

1.2 V for core and peripheral circuitry

Power to match line1.2 V to 1.0 V

Supply voltage for I/O buffer = 2.5 V

8 50% of VCCQ

104 0 V Ground level

1 2.5 V

1 0 V Ground level for PLL

Follow the table below to input F_SEL depending on the CLK operation frequency range

Table 1 F_SEL Input Value for CLK Operation Frequency Range

Input CLK (MHz)

250 to 350

150 to 225

125 to 175

75 to 112.5

F_SEL [2]

0

0

0

0

F_SEL [1]

1

1

0

0

F_SEL [0]

1

0

1

0

Rev.1.00 Feb 21, 2005 page 9 of 14

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