74ALVCH16952 查看數據表（PDF） - Philips Electronics

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74ALVCH16952

16-bit registered transceiver (3-State)

Philips Electronics 

Philips Semiconductors

16-bit registered transceiver (3-State)

Preliminary specification

74ALVCH16952

FEATURES

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through pin-out architecture

• Low inductance, multiple center power and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• Output drive capability 50Ω transmission lines @ 85°C

DESCRIPTION

The 74ALVCH16952 consists of two sections, each containing a

dual octal non-inverting registered transceiver. Two 8-bit back to

back registers store data flowing in both directions between two

bi-directional busses. Data applied to the inputs is entered and

stored on the rising edge of the clock (CPXX, where X is AB or BA)

provided that the clock enable (CEXX) is LOW. The data is then

present at the 3-State output buffers, but is only accessible when the

output enable input (OEXX) is LOW. Data flow from A inputs to B

outputs is the same as for B inputs to A outputs.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf = 2.5ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

fMAX

Propagation delay

CPnn, to An, Bn

Maximum clock frequency

VCC = 3.3V, CL = 50pF

VCC = 2.5V, CL = 30pF

CI

Input capacitance

CPD

Power dissipation capacitance per buffer

VI = GND to VCC1

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL × VCC2 × fo) = sum of outputs.

TYPICAL

3.2

350

3.0

30

UNIT

ns

MHz

pF

pF

ORDERING INFORMATION

PACKAGES

56-Pin Plastic TSSOP Type II

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +85°C

74ALVCH16952 DGG

NORTH AMERICA

ACH16952 DGG

DWG NUMBER

SOT364-1

FUNCTION TABLE for register An or Bn

INPUTS

An or Bn CPXX

X

X

CEXX

H

INTERNAL

Q

NC

OPERATING

MODE

Hold data

L

°

L

L

Load data

H

°

L

H

H = HIGH voltage level

L = LOW voltage level

↑ = LOW-to-HIGH transition

Load data

FUNCTION TABLE for output enable

INPUTS

OEnn

H

INTERNAL

Q

X

An or Bn

OUTPUTS

Z

OPERATING

MODE

Disable outputs

L

L

L

Enable outputs

L

H

H

NC = no change

X = don’t care

Z = high impedance OFF-state

Enable outputs

1998 Sep 01

2

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