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AN6846

Applying SG6846 to Control a Flyback Power Supply with Surge Current Output

Fairchild Semiconductor 

AN-6846

APPLICATION NOTE

Printed Circuit Board (PCB) Layout

High-frequency switching current/voltage makes PCB layout

a very important design issue. Good PCB layout minimizes

excessive EMI and helps the power supply survive during

surge/ESD tests.

Guidelines:

ƒ To get better EMI performance and reduce line

frequency ripples, the output of the bridge rectifier

should be connected to capacitor C1 first, then to the

switching circuits.

ƒ The high-frequency current loop is in C1 –

Transformer – MOSFET – RS – C1. The area

enclosed by this current loop should be as small as

possible. Keep the traces (especially 4→1) short, direct,

and wide. High-voltage traces related to the drain of

MOSFET and RCD snubber should be kept far way

from control circuits to prevent unnecessary

interference. If a heatsink is used for the MOSFET,

connect this heatsink to ground.

ƒ As indicated by 3, the ground of control circuits should

be connected first, then to other circuitry.

ƒ As indicated by 2, the area enclosed by transformer

auxiliary winding, D1, C2, D2, and C3 should also be

kept small. Place C3 close to the SG6846 for good

decoupling.

Two suggestions with different pro and cons for ground

connections are offered:

ƒ GND3 → 2 → 4 → 1: This could avoid common

impedance interference for sense signal.

ƒ GND3→2→1→4: This could be better for ESD testing

where the earth ground is not available on the power

supply. Regarding the ESD discharge path, the charges

go from secondary through the transformer stray

capacitance to GND2 first. The charges then go from

GND2 to GND1 and back to the mains. Note that

control circuits should not be placed on the discharge

path. Point discharge for common choke can decrease

high-frequency impedance and help increase ESD

immunity.

ƒ Should a Y-cap between primary and secondary be

required, connect this Y-cap to the positive terminal of

C1. If this Y-cap is connected to the primary GND, it

should be connected to the negative terminal of C1

(GND1) directly. Point discharge of this Y-cap also

helps for ESD. However, the creepage between these

two pointed ends should be large enough to satisfy the

requirements of applicable standards.

© 2008 Fairchild Semiconductor Corporation

Rev. 1.3.2 • 9/26/08

Figure 16.Layout Considerations

7

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