AD7846(RevE) 查看數據表（PDF） - Analog Devices
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AD7846 Datasheet PDF : 16 Pages
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PIN CONFIGURATIONS
DIP
DB2 1
28 DB3
DB1 2
27 DB4
DB0 3
26 DB5
VDD 4
25 LDAC
VOUT 5
24 CLR
RIN
VREF+
VREF–
6 AD7846 23 CS
7 TOP VIEW 22 R/W
8 (Not to Scale) 21 VCC
VSS 9
20 DGND
DB15 10
19 DB6
DB14 11
18 DB7
DB13 12
17 DB8
DB12 13
16 DB9
DB11 14
15 DB10
PLCC
4 3 2 1 28 27 26
VOUT 5
RIN 6
VREF+ 7
VREF– 8
VSS 9
DB15 10
DB14 11
PIN 1
IDENTIFIER
AD7846
TOP VIEW
(Not to Scale)
25 LDAC
24 CLR
23 CS
22 R/W
21 VCC
20 DGND
19 DB6
12 13 14 15 16 17 18
AD7846
PIN FUNCTION DESCRIPTION
Pin Mnemonic
1–3 DB2–DB0
4
VDD
5
VOUT
6
RIN
7
VREF+
8
VREF–
9
VSS
10–19 DB15–DB6
20 DGND
21
VCC
22 R/W
23 CS
24 CLR
25 LDAC
26–28 DB5–DB3
Description
Data I/O pins. DB0 is LSB.
Positive supply for analog circuitry. This is
+15 V nominal.
DAC output voltage pin.
Input to summing resistor of DAC output
amplifier. This is used to select output
voltage ranges. See Table I.
VREF+ Input. The DAC is specified for VREF+
= +5 V.
VREF– Input. For unipolar operation con-
nect VREF– to 0 V and for bipolar operation
connect it to –5 V. The device is specified
for both conditions.
Negative supply for the analog circuitry.
This is –15 V nominal.
Data I/O pins. DB15 is MSB.
Ground pin for digital circuitry.
Positive supply for digital circuitry. This is
+5 V nominal.
R/W input. This can be used to load data to
the DAC or to read back the DAC latch
contents.
Chip select input. This selects the device.
Clear input. The DAC can be cleared to
000 . . . 000 or 100 . . . 000. See Table II.
Asynchronous load input to DAC.
Data I/O pins.
Table I. Output Voltage Ranges
Output Range
0 V to +5 V
0 V to +10 V
+5 V to –5 V
+5 V to –5 V
+10 V to –10 V
VREF+
+5 V
+5 V
+5 V
+5 V
+5 V
VREF–
0V
0V
–5 V
0V
–5 V
RIN
VOUT
0V
VOUT
+5 V
0V
REV. E
–5–
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