AD7846(RevE) 查看數據表（PDF） - Analog Devices
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AD7846 Datasheet PDF : 16 Pages
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AD7846
VREF+
DAC1
S1
S3
S15
S17
VREF–
DB15–DB12
SEGMENT 16
DAC2
S2
S4
A1
S14
S16
A2
DB15–DB12
SEGMENT 1
DAC3
12 BIT DAC
DB11–DB0
Figure 16. D/A Conversion
R
RIN
R
A3
VOUT
Output Stage
The output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2 kΩ/1000 pF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 µs
after the leading edge of LDAC. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. So, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
without and with the deglitcher.
RIN
10k⍀
10k⍀
C1
DAC3
VOUT
ONE
SHOT
LDAC
Figure 17. Output Stage
UNIPOLAR BINARY OPERATION
Figure 18 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, +5 V refer-
ence. Since RIN is tied to 0 V, the output amplifier has a gain of
2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, RIN should be tied to VOUT, configuring the output
stage for a gain of 1. Table III gives the code table for the circuit
of Figure 18.
+15V
+5V
AD586
C1
1F
R1
10k⍀
4
VDD
VREF+
VCC
VOUT
AD7846*
RIN
VREF–
DGND
VOUT
(0V TO +10V)
SIGNAL
VSS
GROUND
*ADDITIONAL PINS
OMITTED FOR CLARITY
–15V
Figure 18. Unipolar Binary Operation
Table III. Code Table for Figure 18
Binary Number
in DAC Latch
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
Analog Output
(VOUT)
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0
NOTE
1 LSB = 10 V/216 = 10 V/65536 = 152 µV.
Offset and gain may be adjusted in Figure 18 as follows: To
adjust offset, disconnect the VREF– input from 0 V, load the
DAC with all 0s and adjust the VREF– voltage until VOUT = 0 V.
For gain adjustment, the AD7846 should be loaded with all 1s
and R1 adjusted until VOUT = 10 (65535)/(65536) = 9.999847 V.
If a simple resistor divider is used to vary the VREF– voltage, it is
important that the temperature coefficients of these resistors
match that of the DAC input resistance (–300 ppm/°C). Other-
wise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 8 (VREF– ) of the AD7846 tied to 0 V.
–8–
REV. E
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