AD7846(RevE) 查看數據表（PDF） - Analog Devices
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AD7846 Datasheet PDF : 16 Pages
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AD7846
These characteristics are included for design guidance and are not
AC PERFORMANCE CHARACTERISTICS subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V
to –15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V.)
Limit at
Parameter
TMIN to TMAX
(All Versions)
Unit
Test Conditions/Comments
Output Settling Time1
6
9
Slew Rate
7
Digital-to-Analog Glitch
Impulse
70
AC Feedthrough
0.5
Digital Feedthrough
10
Output Noise Voltage
Density 1 kHz–100 kHz 50
µs max
µs max
V/µs typ
To 0.006% FSR. VOUT loaded. VREF– = 0 V. Typically 3.5 µs.
To 0.003% FSR. VOUT loaded. VREF– = –5 V. Typically 6.5 µs.
nV-secs typ
mV pk-pk typ
nV-secs typ
DAC alternately loaded with 10 . . . 0000 and
01 . . . 1111. VOUT unloaded.
VREF– = 0 V, VREF+ = 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s.
DAC alternately loaded with all 1s and all 0s. CS High.
nV/√Hz typ
Measured at VOUT. DAC loaded with 0111011 . . . 11.
VREF+ = VREF– = 0 V.
NOTES
1LDAC = 0. Settling time does not include deglitching time of 2.5 µs (typ).
Specifications subject to change without notice.
TIMING CHARACTERISTICS (VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V)
Parameter
Limit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
t1
0
t2
60
t3
0
t4
60
t5
0
t6
120
t7
10
60
t8
0
t9
70
t10
0
t11
70
t12
130
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
R/W to CS Setup Time
CS Pulsewidth (Write Cycle)
R/W to CS Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Bus Relinquish Time
CLR Setup Time
CLR Pulsewidth
CLR Hold Time
LDAC Pulsewidth
CS Pulsewidth (Read Cycle)
NOTES
1Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.
2t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
DBN
3k⍀
DGND
100pF
DBN
5V
3k⍀
100pF
DGND
a. High Z to VOH
b. High Z to VOL
Figure 1. Load Circuits for Access Time (t6)
5V
DBN
3k⍀
DGND
10pF
DBN
3k⍀
10pF
DGND
a. VOH to High Z
b. VOL to High Z
Figure 2. Load Circuits for Bus Relinquish Time (t7)
R/ W
CS
DATA
CLR
LDAC
t1
t3
t1
t3
t2
t4
DATA VALID
t8
t9
t5
t 10
t 12
t6
t7
DATA VALID
t8
tt99
t 10
Figure 3. Timing Diagram
5V
0V
5V
0V
5V
0V
5V
0V
t 11
5V
0V
REV. E
–3–
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