AD7846 查看數據表（PDF） - Analog Devices
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AD7846 Datasheet PDF : 24 Pages
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AD7846
TIMING CHARACTERISTICS
VDD = +14.25 V to +15.75 V, VSS = −14.25 V to −15.75 V, VCC = +4.75 V to +5.25 V, unless otherwise noted.
Table 3.
Parameter1
t1
t2
t3
t4
t5
t6 2
t7 3
t8
t9
t10
t11
t12
Limit at TMIN to TMAX (All Versions)
0
60
0
60
0
120
10
60
0
70
0
70
130
Unit
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
R/W to CS setup time
CS pulse width (write cycle)
R/W to CS hold time
Data setup time
Data hold time
Data access time
Bus relinquish time
CLR setup time
CLR pulse width
CLR hold time
LDAC pulse width
CS pulse width (read cycle)
1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a
voltage level of 1.6 V.
2 t6 is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3 t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6.
R/W
CS
DB0
TO
DB15
CLR
LDAC
t1
t3
t2
t4
t5
DATA VALID
t8
t9
t10
t1
t3
t12
t6
t7
DATA VALID
t8
t9
t10
Figure 2. Timing Diagram
5V
0V
5V
0V
5V
0V
5V
0V
t11
5V
0V
DBn
3kΩ
DGND
100pF
DBn
3kΩ
DGND
10pF
Figure 3. Load Circuit for Access Time (t6)—High Z to VOH
Figure 5. Load Circuit for Access Time (t7)—High Z to VOH
DBn
5V
3kΩ
100pF
DGND
Figure 4. Load Circuits for Bus Relinquish Time (t6)—High Z to VOL
5V
DBn
3kΩ
10pF
DGND
Figure 6. Load Circuits for Bus Relinquish Time (t7)—High Z to VOL
Rev. G | Page 5 of 24
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