SPT5400SCP 查看數據表（PDF） - Cadeka Microcircuits LLC.
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SPT5400SCP Datasheet PDF : 8 Pages
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GENERAL CIRCUIT DESCRIPTION
The SPT5400 contains eight 13-bit, voltage-output
DACs. It uses a novel circuit topology to convert the
13-bit digital inputs into equivalent output voltages that
are proportionate to the applied reference voltages. The
SPT5400 has four separate reference voltage (REFxx)
and analog ground (AGNDxx) inputs for each DAC pair.
The REFxx inputs allow for separate full-scale output
voltages for each DAC pair. The AGNDxx inputs allow for
separate offset voltages for each DAC pair.
VOLTAGE REFERENCE AND ANALOG
GROUND INPUTS
The REFxx and AGNDxx inputs set the output range of
the corresponding DAC pair. For a detailed description of
the relationship between the DAC output range and the
REFxx and AGNDxx input voltages, see the Analog Out-
puts section of this datasheet.
The reference input impedance is code dependent. It is at
its highest value when the input code of the correspond-
ing DAC pair is all 1s. It is at its lowest value when the
input code is all 0s. Because the input impedance is code
dependent, load regulation of the reference is critical.
MULTIPLYING OPERATION
Because the reference of the SPT5400 accepts both AC
and DC signals, it can be used for multiplying applica-
tions. The REFxx inputs (which set the full-scale output
voltage for the respective DACs) only accept positive
voltages, so the multiplying operation is limited to two
quadrants. Note that when applying AC signals to the ref-
erence, do not bypass the inputs.
DIGITAL INPUTS AND
MICROPROCESSOR INTERFACE
All digital inputs are TTL/CMOS compatible. The
SPT5400 is compatible with microprocessors having a
minimum 13-bit-wide data bus. The microprocessor inter-
face is double-buffered to allow all the DACs to be simul-
taneously updated.
DAC ADDRESSING AND LATCHING
Each DAC has an input latch that receives data from the
data bus, and a DAC latch that receives data from the
input latch. The address lines (A0–A2) for each DAC in-
put latch are shown in table II. Data is transferred from
the input latch to the DAC latch when LDxx is asserted.
The analog output of each DAC reflects the data held in
its corresponding DAC latch. In addition to being latched,
data can be transferred to the DAC directly through
transparent latches.
Table II – DAC Addressing
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Function
DAC A input latch
DAC B input latch
DAC C input latch
DAC D input latch
DAC E input latch
DAC F input latch
DAC G input latch
DAC H input latch
The control inputs of the SPT5400 are level triggered,
and are shown in table III. The input latch is controlled by
CS and WR, and the transfer of data to the DAC latch is
controlled by LDxx. When CS and WR are low, the input
latch is transparent. When LDxx is low the DAC latch is
transparent. To avoid transferring data to the wrong DAC,
the address lines (A0–A2) must be valid through the time
CS and WR are low. See the timing diagram for specific
timing values. When CS and WR are high, the data is
latched into the input latch. When LDxx is high, the data is
latched into the DAC latch. If LDxx is low when CS and WR
are low, then it must be held low for t3 or longer after CS or
WR goes high.
When CLR is low, all DAC outputs are set to their corre-
sponding AGNDxx. When CLR toggles from low to high,
1000hex is latched into all input and DAC latches.
Table III – Interface Truth Table
CLR LDxx WR CS Function
1 0 0 0 Both latches transparent
1 1 1 x Both latches latched
1 1 x 1 Both latches latched
1 x 0 0 Input latch transparent
1 x 1 x Input latch latched
1 x x 1 Input latch latched
1 0 x x DAC latch transparent
0 x x x All input and DAC latches at
1000hex, outputs at AGNDxx
DIGITAL CODE
The SPT5400 uses offset binary coding. Conversion to a
13-bit offset binary code from a 13-bit twos-complement
code can be achieved by adding 212 = 4096.
SPT5400
4
5/15/00
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